f1bfed10ad
In rustc (and I suspect Clang and Zig) there is some special logic to rewrite `r14` into `lr` when used in inline assembly. LLVM should probably support `r14` directly. https://developer.arm.com/documentation/ddi0211/i/programmer-s-model/registers/the-arm-state-register-set > You can treat r14 as a general-purpose register at all other times. This heavily suggests that we should be able to use it as a clobber and read its value. This is the arm analogue to https://github.com/llvm/llvm-project/pull/167783.
60 lines
2.1 KiB
LLVM
60 lines
2.1 KiB
LLVM
; RUN: llc <%s -mtriple=arm-none-eabi 2>&1 | FileCheck %s -check-prefix=CHECK
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; RUN: llc <%s -mtriple=arm-none-eabi -relocation-model=rwpi 2>&1 \
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; RUN: | FileCheck %s -check-prefix=RWPI
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; RUN: llc <%s -mtriple=arm-none-eabi --frame-pointer=all 2>&1 \
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; RUN: | FileCheck %s -check-prefix=NO_FP_ELIM
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; RUN: llc <%s -mtriple=armv6-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2
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; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2
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; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3
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; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS3
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; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC
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; CHECK: warning: inline asm clobber list contains reserved registers: R11
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; RWPI: warning: inline asm clobber list contains reserved registers: R9, SP, PC
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; RWPI: warning: inline asm clobber list contains reserved registers: R11
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; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC
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; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11
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; IOS2: warning: inline asm clobber list contains reserved registers: R9, SP, PC
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; IOS3: warning: inline asm clobber list contains reserved registers: SP, PC
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define void @foo() nounwind {
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call void asm sideeffect "mov r7, #1",
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"~{r9},~{r11},~{r12},~{lr},~{sp},~{pc},~{r10}"()
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ret void
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}
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define i32 @bar(i32 %i) {
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%vla = alloca i32, i32 %i, align 4
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tail call void asm sideeffect "mov r7, #1", "~{r11}"()
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%1 = load volatile i32, ptr %vla, align 4
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ret i32 %1
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}
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; r14 is an alias for lr.
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define void @clobber_r14() nounwind {
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; CHECK-LABEL: clobber_r14:
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; CHECK: .save {r11, lr}
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; CHECK: push {r11, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r11, lr}
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tail call void asm sideeffect "", "~{r14}"()
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ret void
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}
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; r14 is an alias for lr.
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define i32 @read_r14() nounwind {
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start:
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; CHECK-LABEL: read_r14:
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; CHECK: push {r11, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: mov r0, lr
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; CHECK-NEXT: pop {r11, lr}
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%1 = tail call i32 asm sideeffect alignstack "", "=&{r14},~{cc},~{memory}"()
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ret i32 %1
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}
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