0b36d4265e
This patch teaches the backend how to lower the FCBRT DAG node to the vector math library function when using ArmPL. This is similar to what we already do for llvm.pow/FPOW, however the only way to expose this is via a DAG combine that converts FPOW(<2 x double> %x, <2 x double> <double 1.0/3.0, double 1.0/3.0>) into FCBRT(<2 x double> %x) when the appropriate fast math flags are present on the node. I've updated the DAG combine to handle vector types and only perform the transformation if there exists a vector library variant of cbrt.
123 lines
4.0 KiB
LLVM
123 lines
4.0 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefixes=ANY,SOFTFLOAT
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; RUN: llc < %s -mtriple=thumbv8-linux-gnueabihf -mattr=neon | FileCheck %s --check-prefixes=ANY,HARDFLOAT
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declare float @llvm.pow.f32(float, float)
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declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
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declare double @llvm.pow.f64(double, double)
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declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
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define float @pow_f32_one_fourth_fmf(float %x) nounwind {
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; ANY-LABEL: pow_f32_one_fourth_fmf:
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; SOFTFLOAT: bl powf
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
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ret float %r
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}
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define double @pow_f64_one_fourth_fmf(double %x) nounwind {
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; ANY-LABEL: pow_f64_one_fourth_fmf:
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; SOFTFLOAT: bl pow
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; HARDFLOAT: vsqrt.f64
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; HARDFLOAT: vsqrt.f64
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%r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01)
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ret double %r
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}
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define float @pow_f32_one_third_fmf(float %x) nounwind {
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; ANY-LABEL: pow_f32_one_third_fmf:
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; SOFTFLOAT: bl cbrtf
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; HARDFLOAT: b cbrtf
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%r = call fast float @llvm.pow.f32(float %x, float 0x3FD5555560000000)
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ret float %r
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}
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define double @pow_f64_one_third_fmf(double %x) nounwind {
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; ANY-LABEL: pow_f64_one_third_fmf:
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; SOFTFLOAT: bl cbrt
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; HARDFLOAT: b cbrt
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%r = call fast double @llvm.pow.f64(double %x, double 0x3FD5555555555555)
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ret double %r
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}
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define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind {
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; ANY-LABEL: pow_v4f32_one_fourth_fmf:
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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; HARDFLOAT: vsqrt.f32
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%r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
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ret <4 x float> %r
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}
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define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind {
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; ANY-LABEL: pow_v2f64_one_fourth_fmf:
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; SOFTFLOAT: bl pow
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; SOFTFLOAT: bl pow
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; HARDFLOAT: vsqrt.f64
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; HARDFLOAT: vsqrt.f64
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; HARDFLOAT: vsqrt.f64
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; HARDFLOAT: vsqrt.f64
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%r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
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ret <2 x double> %r
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}
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define float @pow_f32_one_fourth_not_enough_fmf(float %x) nounwind {
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; ANY-LABEL: pow_f32_one_fourth_not_enough_fmf:
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; SOFTFLOAT: bl powf
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; HARDFLOAT: b powf
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%r = call afn ninf float @llvm.pow.f32(float %x, float 2.5e-01)
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ret float %r
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}
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define double @pow_f64_one_fourth_not_enough_fmf(double %x) nounwind {
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; ANY-LABEL: pow_f64_one_fourth_not_enough_fmf:
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; SOFTFLOAT: bl pow
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; HARDFLOAT: b pow
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%r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01)
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ret double %r
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}
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define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind {
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; ANY-LABEL: pow_v4f32_one_fourth_not_enough_fmf:
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; ANY: bl powf
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; ANY: bl powf
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; ANY: bl powf
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; ANY: bl powf
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%r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
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ret <4 x float> %r
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}
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define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind {
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; ANY-LABEL: pow_v2f64_one_fourth_not_enough_fmf:
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; ANY: bl pow
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; ANY: bl pow
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%r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
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ret <2 x double> %r
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}
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define <4 x float> @test_pow_one_third_v4f32(<4 x float> %x) nounwind {
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; SOFTFLOAT-LABEL: test_pow_one_third_v4f32:
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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; SOFTFLOAT: bl powf
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;
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; HARDFLOAT-LABEL: test_pow_one_third_v4f32:
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; HARDFLOAT: bl cbrtf
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; HARDFLOAT: bl cbrtf
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; HARDFLOAT: bl cbrtf
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; HARDFLOAT: bl cbrtf
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%r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> splat (float 0x3FD5555560000000))
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ret <4 x float> %r
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}
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