2696 lines
89 KiB
LLVM
2696 lines
89 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-ARM
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; RUN: llc -mtriple=armv7eb-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-BE
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; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-THUMB
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; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-THUMB
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; RUN: llc -mtriple=thumbv7m -mattr=+strict-align %s -o - | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-ALIGN
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; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M
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@array = weak global [4 x i32] zeroinitializer
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define i32 @test_lshr_and1(i32 %x) {
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; CHECK-COMMON-LABEL: test_lshr_and1:
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; CHECK-COMMON: @ %bb.0: @ %entry
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; CHECK-COMMON-NEXT: movw r1, :lower16:array
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; CHECK-COMMON-NEXT: and r0, r0, #12
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; CHECK-COMMON-NEXT: movt r1, :upper16:array
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; CHECK-COMMON-NEXT: ldr r0, [r1, r0]
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; CHECK-COMMON-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_and1:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: movw r1, :lower16:array
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; CHECK-BE-NEXT: and r0, r0, #12
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; CHECK-BE-NEXT: movt r1, :upper16:array
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; CHECK-BE-NEXT: ldr r0, [r1, r0]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_and1:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: movs r1, #12
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; CHECK-V6M-NEXT: ands r1, r0
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; CHECK-V6M-NEXT: ldr r0, .LCPI0_0
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; CHECK-V6M-NEXT: ldr r0, [r0, r1]
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; CHECK-V6M-NEXT: bx lr
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; CHECK-V6M-NEXT: .p2align 2
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; CHECK-V6M-NEXT: @ %bb.1:
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; CHECK-V6M-NEXT: .LCPI0_0:
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; CHECK-V6M-NEXT: .long array
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entry:
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%tmp2 = lshr i32 %x, 2
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%tmp3 = and i32 %tmp2, 3
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%tmp4 = getelementptr [4 x i32], ptr @array, i32 0, i32 %tmp3
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%tmp5 = load i32, ptr %tmp4, align 4
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ret i32 %tmp5
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}
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define i32 @test_lshr_and2(i32 %x) {
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; CHECK-ARM-LABEL: test_lshr_and2:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ubfx r0, r0, #1, #15
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; CHECK-ARM-NEXT: add r0, r0, r0
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_and2:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ubfx r0, r0, #1, #15
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; CHECK-BE-NEXT: add r0, r0, r0
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_and2:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ubfx r0, r0, #1, #15
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; CHECK-THUMB-NEXT: add r0, r0
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_and2:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ubfx r0, r0, #1, #15
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; CHECK-ALIGN-NEXT: add r0, r0
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_and2:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: lsls r0, r0, #16
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; CHECK-V6M-NEXT: lsrs r0, r0, #17
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; CHECK-V6M-NEXT: adds r0, r0, r0
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; CHECK-V6M-NEXT: bx lr
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entry:
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%a = and i32 %x, 65534
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%b = lshr i32 %a, 1
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%c = and i32 %x, 65535
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%d = lshr i32 %c, 1
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%e = add i32 %b, %d
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ret i32 %e
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}
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define arm_aapcscc i32 @test_lshr_load1(ptr %a) {
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; CHECK-COMMON-LABEL: test_lshr_load1:
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; CHECK-COMMON: @ %bb.0: @ %entry
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; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]
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; CHECK-COMMON-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load1:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldrb r0, [r0]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load1:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrb r0, [r0, #1]
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i16, ptr %a, align 2
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%conv1 = zext i16 %0 to i32
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%1 = lshr i32 %conv1, 8
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load1_sext(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load1_sext:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldrsh r0, [r0]
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; CHECK-ARM-NEXT: lsr r0, r0, #8
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load1_sext:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldrsh r0, [r0]
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; CHECK-BE-NEXT: lsr r0, r0, #8
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load1_sext:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldrsh.w r0, [r0]
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; CHECK-THUMB-NEXT: lsrs r0, r0, #8
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load1_sext:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldrsh.w r0, [r0]
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; CHECK-ALIGN-NEXT: lsrs r0, r0, #8
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load1_sext:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: movs r1, #0
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; CHECK-V6M-NEXT: ldrsh r0, [r0, r1]
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; CHECK-V6M-NEXT: lsrs r0, r0, #8
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i16, ptr %a, align 2
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%conv1 = sext i16 %0 to i32
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%1 = lshr i32 %conv1, 8
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load1_fail(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load1_fail:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldrh r0, [r0]
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; CHECK-ARM-NEXT: lsr r0, r0, #9
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load1_fail:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldrh r0, [r0]
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; CHECK-BE-NEXT: lsr r0, r0, #9
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load1_fail:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldrh r0, [r0]
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; CHECK-THUMB-NEXT: lsrs r0, r0, #9
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load1_fail:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldrh r0, [r0]
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; CHECK-ALIGN-NEXT: lsrs r0, r0, #9
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load1_fail:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrh r0, [r0]
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; CHECK-V6M-NEXT: lsrs r0, r0, #9
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i16, ptr %a, align 2
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%conv1 = zext i16 %0 to i32
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%1 = lshr i32 %conv1, 9
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load32(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load32:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldr r0, [r0]
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; CHECK-ARM-NEXT: lsr r0, r0, #8
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load32:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldr r0, [r0]
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; CHECK-BE-NEXT: lsr r0, r0, #8
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load32:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldr r0, [r0]
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; CHECK-THUMB-NEXT: lsrs r0, r0, #8
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load32:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldr r0, [r0]
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; CHECK-ALIGN-NEXT: lsrs r0, r0, #8
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load32:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldr r0, [r0]
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; CHECK-V6M-NEXT: lsrs r0, r0, #8
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i32, ptr %a, align 4
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%1 = lshr i32 %0, 8
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load32_2(ptr %a) {
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; CHECK-COMMON-LABEL: test_lshr_load32_2:
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; CHECK-COMMON: @ %bb.0: @ %entry
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; CHECK-COMMON-NEXT: ldrh r0, [r0, #2]
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; CHECK-COMMON-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load32_2:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldrh r0, [r0]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load32_2:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrh r0, [r0, #2]
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i32, ptr %a, align 4
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%1 = lshr i32 %0, 16
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load32_1(ptr %a) {
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; CHECK-COMMON-LABEL: test_lshr_load32_1:
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; CHECK-COMMON: @ %bb.0: @ %entry
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; CHECK-COMMON-NEXT: ldrb r0, [r0, #3]
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; CHECK-COMMON-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load32_1:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldrb r0, [r0]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load32_1:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrb r0, [r0, #3]
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i32, ptr %a, align 4
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%1 = lshr i32 %0, 24
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load32_fail(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load32_fail:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldr r0, [r0]
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; CHECK-ARM-NEXT: lsr r0, r0, #15
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load32_fail:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldr r0, [r0]
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; CHECK-BE-NEXT: lsr r0, r0, #15
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load32_fail:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldr r0, [r0]
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; CHECK-THUMB-NEXT: lsrs r0, r0, #15
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load32_fail:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldr r0, [r0]
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; CHECK-ALIGN-NEXT: lsrs r0, r0, #15
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load32_fail:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldr r0, [r0]
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; CHECK-V6M-NEXT: lsrs r0, r0, #15
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i32, ptr %a, align 4
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%1 = lshr i32 %0, 15
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ret i32 %1
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}
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define arm_aapcscc i32 @test_lshr_load64_4_unaligned(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load64_4_unaligned:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldr r0, [r0, #2]
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load64_4_unaligned:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldr r0, [r0, #2]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load64_4_unaligned:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldr.w r0, [r0, #2]
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load64_4_unaligned:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldr r1, [r0, #4]
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; CHECK-ALIGN-NEXT: ldrh r0, [r0, #2]
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; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #16
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load64_4_unaligned:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrh r1, [r0, #2]
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; CHECK-V6M-NEXT: ldr r0, [r0, #4]
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; CHECK-V6M-NEXT: lsls r0, r0, #16
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; CHECK-V6M-NEXT: adds r0, r1, r0
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i64, ptr %a, align 8
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%1 = lshr i64 %0, 16
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%conv = trunc i64 %1 to i32
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ret i32 %conv
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}
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define arm_aapcscc i32 @test_lshr_load64_1_lsb(ptr %a) {
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; CHECK-ARM-LABEL: test_lshr_load64_1_lsb:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: ldr r0, [r0, #3]
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_lshr_load64_1_lsb:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: ldr r0, [r0, #1]
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; CHECK-BE-NEXT: bx lr
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;
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; CHECK-THUMB-LABEL: test_lshr_load64_1_lsb:
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; CHECK-THUMB: @ %bb.0: @ %entry
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; CHECK-THUMB-NEXT: ldr.w r0, [r0, #3]
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; CHECK-THUMB-NEXT: bx lr
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;
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; CHECK-ALIGN-LABEL: test_lshr_load64_1_lsb:
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; CHECK-ALIGN: @ %bb.0: @ %entry
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; CHECK-ALIGN-NEXT: ldr r1, [r0, #4]
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; CHECK-ALIGN-NEXT: ldrb r0, [r0, #3]
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; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #8
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; CHECK-ALIGN-NEXT: bx lr
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;
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; CHECK-V6M-LABEL: test_lshr_load64_1_lsb:
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; CHECK-V6M: @ %bb.0: @ %entry
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; CHECK-V6M-NEXT: ldrb r1, [r0, #3]
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; CHECK-V6M-NEXT: ldr r0, [r0, #4]
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; CHECK-V6M-NEXT: lsls r0, r0, #8
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; CHECK-V6M-NEXT: adds r0, r1, r0
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; CHECK-V6M-NEXT: bx lr
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entry:
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%0 = load i64, ptr %a, align 8
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%1 = lshr i64 %0, 24
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%conv = trunc i64 %1 to i32
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ret i32 %conv
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}
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define arm_aapcscc i32 @test_lshr_load64_1_msb(ptr %a) {
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; CHECK-COMMON-LABEL: test_lshr_load64_1_msb:
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; CHECK-COMMON: @ %bb.0: @ %entry
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; CHECK-COMMON-NEXT: ldrb r0, [r0, #7]
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; CHECK-COMMON-NEXT: bx lr
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;
|
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; CHECK-BE-LABEL: test_lshr_load64_1_msb:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_lshr_load64_1_msb:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r0, [r0, #7]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i64, ptr %a, align 8
|
|
%1 = lshr i64 %0, 56
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_lshr_load64_4(ptr %a) {
|
|
; CHECK-COMMON-LABEL: test_lshr_load64_4:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldr r0, [r0, #4]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_lshr_load64_4:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r0, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_lshr_load64_4:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r0, [r0, #4]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i64, ptr %a, align 8
|
|
%1 = lshr i64 %0, 32
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_lshr_load64_2(ptr %a) {
|
|
; CHECK-COMMON-LABEL: test_lshr_load64_2:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldrh r0, [r0, #6]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_lshr_load64_2:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrh r0, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_lshr_load64_2:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrh r0, [r0, #6]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i64, ptr %a, align 8
|
|
%1 = lshr i64 %0, 48
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_lshr_load4_fail(ptr %a) {
|
|
; CHECK-ARM-LABEL: test_lshr_load4_fail:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldr r0, [r0, #1]
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_lshr_load4_fail:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r0, [r0, #3]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_lshr_load4_fail:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldr.w r0, [r0, #1]
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_lshr_load4_fail:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrd r0, r1, [r0]
|
|
; CHECK-ALIGN-NEXT: lsrs r0, r0, #8
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #24
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_lshr_load4_fail:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: ldr r0, [r0, #4]
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #24
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #8
|
|
; CHECK-V6M-NEXT: adds r0, r1, r0
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i64, ptr %a, align 8
|
|
%1 = lshr i64 %0, 8
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift7_mask8(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift7_mask8:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldr r1, [r0]
|
|
; CHECK-COMMON-NEXT: ubfx r1, r1, #7, #8
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift7_mask8:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: ubfx r1, r1, #7, #8
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift7_mask8:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #7
|
|
; CHECK-V6M-NEXT: uxtb r1, r1
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 7
|
|
%and = and i32 %shl, 255
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift8_mask8(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift8_mask8:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldrb r1, [r0, #1]
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift8_mask8:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r1, [r0, #2]
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift8_mask8:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r1, [r0, #1]
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 8
|
|
%and = and i32 %shl, 255
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift8_mask7(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift8_mask7:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldr r1, [r0]
|
|
; CHECK-COMMON-NEXT: ubfx r1, r1, #8, #7
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift8_mask7:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: ubfx r1, r1, #8, #7
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift8_mask7:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsls r1, r1, #17
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #25
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 8
|
|
%and = and i32 %shl, 127
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift9_mask8(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift9_mask8:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldr r1, [r0]
|
|
; CHECK-COMMON-NEXT: ubfx r1, r1, #9, #8
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift9_mask8:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: ubfx r1, r1, #9, #8
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift9_mask8:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #9
|
|
; CHECK-V6M-NEXT: uxtb r1, r1
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 9
|
|
%and = and i32 %shl, 255
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift8_mask16(ptr nocapture %p) {
|
|
; CHECK-ARM-LABEL: test_shift8_mask16:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrh r1, [r0, #1]
|
|
; CHECK-ARM-NEXT: str r1, [r0]
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift8_mask16:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrh r1, [r0, #1]
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_shift8_mask16:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrh.w r1, [r0, #1]
|
|
; CHECK-THUMB-NEXT: str r1, [r0]
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_shift8_mask16:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldr r1, [r0]
|
|
; CHECK-ALIGN-NEXT: ubfx r1, r1, #8, #16
|
|
; CHECK-ALIGN-NEXT: str r1, [r0]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift8_mask16:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #8
|
|
; CHECK-V6M-NEXT: uxth r1, r1
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 8
|
|
%and = and i32 %shl, 65535
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift15_mask16(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift15_mask16:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldr r1, [r0]
|
|
; CHECK-COMMON-NEXT: ubfx r1, r1, #15, #16
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift15_mask16:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: ubfx r1, r1, #15, #16
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift15_mask16:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #15
|
|
; CHECK-V6M-NEXT: uxth r1, r1
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 15
|
|
%and = and i32 %shl, 65535
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift16_mask15(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift16_mask15:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldrh r1, [r0, #2]
|
|
; CHECK-COMMON-NEXT: bfc r1, #15, #17
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift16_mask15:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrh r1, [r0]
|
|
; CHECK-BE-NEXT: bfc r1, #15, #17
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift16_mask15:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrh r1, [r0, #2]
|
|
; CHECK-V6M-NEXT: ldr r2, .LCPI21_0
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: str r2, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
; CHECK-V6M-NEXT: .p2align 2
|
|
; CHECK-V6M-NEXT: @ %bb.1:
|
|
; CHECK-V6M-NEXT: .LCPI21_0:
|
|
; CHECK-V6M-NEXT: .long 32767 @ 0x7fff
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 16
|
|
%and = and i32 %shl, 32767
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift8_mask24(ptr nocapture %p) {
|
|
; CHECK-ARM-LABEL: test_shift8_mask24:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldr r1, [r0]
|
|
; CHECK-ARM-NEXT: lsr r1, r1, #8
|
|
; CHECK-ARM-NEXT: str r1, [r0]
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift8_mask24:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldr r1, [r0]
|
|
; CHECK-BE-NEXT: lsr r1, r1, #8
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_shift8_mask24:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldr r1, [r0]
|
|
; CHECK-THUMB-NEXT: lsrs r1, r1, #8
|
|
; CHECK-THUMB-NEXT: str r1, [r0]
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_shift8_mask24:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldr r1, [r0]
|
|
; CHECK-ALIGN-NEXT: lsrs r1, r1, #8
|
|
; CHECK-ALIGN-NEXT: str r1, [r0]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift8_mask24:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldr r1, [r0]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #8
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 8
|
|
%and = and i32 %shl, 16777215
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_shift24_mask16(ptr nocapture %p) {
|
|
; CHECK-COMMON-LABEL: test_shift24_mask16:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldrb r1, [r0, #3]
|
|
; CHECK-COMMON-NEXT: str r1, [r0]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift24_mask16:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r1, [r0]
|
|
; CHECK-BE-NEXT: str r1, [r0]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift24_mask16:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r1, [r0, #3]
|
|
; CHECK-V6M-NEXT: str r1, [r0]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i32, ptr %p, align 4
|
|
%shl = lshr i32 %0, 24
|
|
%and = and i32 %shl, 65535
|
|
store i32 %and, ptr %p, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_sext_shift8_mask8(ptr %p, ptr %q) {
|
|
; CHECK-COMMON-LABEL: test_sext_shift8_mask8:
|
|
; CHECK-COMMON: @ %bb.0: @ %entry
|
|
; CHECK-COMMON-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-COMMON-NEXT: str r0, [r1]
|
|
; CHECK-COMMON-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_sext_shift8_mask8:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: str r0, [r1]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_sext_shift8_mask8:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-V6M-NEXT: str r0, [r1]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i16, ptr %p, align 4
|
|
%1 = sext i16 %0 to i32
|
|
%shl = lshr i32 %1, 8
|
|
%and = and i32 %shl, 255
|
|
store i32 %and, ptr %q, align 4
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcscc void @test_sext_shift8_mask16(ptr %p, ptr %q) {
|
|
; CHECK-ARM-LABEL: test_sext_shift8_mask16:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrsh r0, [r0]
|
|
; CHECK-ARM-NEXT: ubfx r0, r0, #8, #16
|
|
; CHECK-ARM-NEXT: str r0, [r1]
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_sext_shift8_mask16:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrsh r0, [r0]
|
|
; CHECK-BE-NEXT: ubfx r0, r0, #8, #16
|
|
; CHECK-BE-NEXT: str r0, [r1]
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_sext_shift8_mask16:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrsh.w r0, [r0]
|
|
; CHECK-THUMB-NEXT: ubfx r0, r0, #8, #16
|
|
; CHECK-THUMB-NEXT: str r0, [r1]
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_sext_shift8_mask16:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrsh.w r0, [r0]
|
|
; CHECK-ALIGN-NEXT: ubfx r0, r0, #8, #16
|
|
; CHECK-ALIGN-NEXT: str r0, [r1]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_sext_shift8_mask16:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: movs r2, #0
|
|
; CHECK-V6M-NEXT: ldrsh r0, [r0, r2]
|
|
; CHECK-V6M-NEXT: lsrs r0, r0, #8
|
|
; CHECK-V6M-NEXT: uxth r0, r0
|
|
; CHECK-V6M-NEXT: str r0, [r1]
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%0 = load i16, ptr %p, align 4
|
|
%1 = sext i16 %0 to i32
|
|
%shl = lshr i32 %1, 8
|
|
%and = and i32 %shl, 65535
|
|
store i32 %and, ptr %q, align 4
|
|
ret void
|
|
}
|
|
|
|
define i1 @trunc_i64_mask_srl(i32 zeroext %AttrArgNo, ptr %ptr) {
|
|
; CHECK-ARM-LABEL: trunc_i64_mask_srl:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrh r2, [r1, #4]
|
|
; CHECK-ARM-NEXT: mov r1, #0
|
|
; CHECK-ARM-NEXT: cmp r2, r0
|
|
; CHECK-ARM-NEXT: movwhi r1, #1
|
|
; CHECK-ARM-NEXT: mov r0, r1
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: trunc_i64_mask_srl:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrh r2, [r1, #2]
|
|
; CHECK-BE-NEXT: mov r1, #0
|
|
; CHECK-BE-NEXT: cmp r2, r0
|
|
; CHECK-BE-NEXT: movwhi r1, #1
|
|
; CHECK-BE-NEXT: mov r0, r1
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: trunc_i64_mask_srl:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrh r2, [r1, #4]
|
|
; CHECK-THUMB-NEXT: movs r1, #0
|
|
; CHECK-THUMB-NEXT: cmp r2, r0
|
|
; CHECK-THUMB-NEXT: it hi
|
|
; CHECK-THUMB-NEXT: movhi r1, #1
|
|
; CHECK-THUMB-NEXT: mov r0, r1
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: trunc_i64_mask_srl:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrh r2, [r1, #4]
|
|
; CHECK-ALIGN-NEXT: movs r1, #0
|
|
; CHECK-ALIGN-NEXT: cmp r2, r0
|
|
; CHECK-ALIGN-NEXT: it hi
|
|
; CHECK-ALIGN-NEXT: movhi r1, #1
|
|
; CHECK-ALIGN-NEXT: mov r0, r1
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: trunc_i64_mask_srl:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrh r1, [r1, #4]
|
|
; CHECK-V6M-NEXT: cmp r1, r0
|
|
; CHECK-V6M-NEXT: bhi .LBB26_2
|
|
; CHECK-V6M-NEXT: @ %bb.1: @ %entry
|
|
; CHECK-V6M-NEXT: movs r0, #0
|
|
; CHECK-V6M-NEXT: bx lr
|
|
; CHECK-V6M-NEXT: .LBB26_2:
|
|
; CHECK-V6M-NEXT: movs r0, #1
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%bf.load.i = load i64, ptr %ptr, align 8
|
|
%bf.lshr.i = lshr i64 %bf.load.i, 32
|
|
%0 = trunc i64 %bf.lshr.i to i32
|
|
%bf.cast.i = and i32 %0, 65535
|
|
%cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
|
|
ret i1 %cmp.i
|
|
}
|
|
|
|
define i64 @or_tree_with_shifts_i64(i64 %a, i64 %b, i64 %c, i64 %d) {
|
|
; CHECK-ARM-LABEL: or_tree_with_shifts_i64:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: .save {r11, lr}
|
|
; CHECK-ARM-NEXT: push {r11, lr}
|
|
; CHECK-ARM-NEXT: ldr lr, [sp, #16]
|
|
; CHECK-ARM-NEXT: orr r0, r0, r2, lsl #16
|
|
; CHECK-ARM-NEXT: ldr r12, [sp, #8]
|
|
; CHECK-ARM-NEXT: orr r3, lr, r3
|
|
; CHECK-ARM-NEXT: orr r1, r1, r3, lsl #16
|
|
; CHECK-ARM-NEXT: orr r1, r1, r2, lsr #16
|
|
; CHECK-ARM-NEXT: orr r1, r1, r12
|
|
; CHECK-ARM-NEXT: pop {r11, pc}
|
|
;
|
|
; CHECK-BE-LABEL: or_tree_with_shifts_i64:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: .save {r11, lr}
|
|
; CHECK-BE-NEXT: push {r11, lr}
|
|
; CHECK-BE-NEXT: ldr lr, [sp, #20]
|
|
; CHECK-BE-NEXT: orr r1, r1, r3, lsl #16
|
|
; CHECK-BE-NEXT: ldr r12, [sp, #12]
|
|
; CHECK-BE-NEXT: orr r2, lr, r2
|
|
; CHECK-BE-NEXT: orr r0, r0, r2, lsl #16
|
|
; CHECK-BE-NEXT: orr r0, r0, r3, lsr #16
|
|
; CHECK-BE-NEXT: orr r0, r0, r12
|
|
; CHECK-BE-NEXT: pop {r11, pc}
|
|
;
|
|
; CHECK-ALIGN-LABEL: or_tree_with_shifts_i64:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsl #16
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsl #16
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsr #16
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp]
|
|
; CHECK-ALIGN-NEXT: orrs r1, r2
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: or_tree_with_shifts_i64:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: lsls r4, r2, #16
|
|
; CHECK-V6M-NEXT: orrs r0, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #16]
|
|
; CHECK-V6M-NEXT: orrs r4, r3
|
|
; CHECK-V6M-NEXT: lsls r3, r4, #16
|
|
; CHECK-V6M-NEXT: orrs r1, r3
|
|
; CHECK-V6M-NEXT: lsrs r2, r2, #16
|
|
; CHECK-V6M-NEXT: orrs r1, r2
|
|
; CHECK-V6M-NEXT: ldr r2, [sp, #8]
|
|
; CHECK-V6M-NEXT: orrs r1, r2
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
%b.shifted = shl i64 %b, 16
|
|
%c.shifted = shl i64 %c, 32
|
|
%d.shifted = shl i64 %d, 48
|
|
%or.ad = or i64 %a, %d.shifted
|
|
%or.adb = or i64 %or.ad, %b.shifted
|
|
%or.adbc = or i64 %or.adb, %c.shifted
|
|
ret i64 %or.adbc
|
|
}
|
|
|
|
define i32 @or_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-ARM-LABEL: or_tree_with_shifts_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: orr r0, r0, r2
|
|
; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #16
|
|
; CHECK-ARM-NEXT: orr r0, r0, r3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: or_tree_with_shifts_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: orr r0, r0, r2
|
|
; CHECK-BE-NEXT: orr r0, r1, r0, lsl #16
|
|
; CHECK-BE-NEXT: orr r0, r0, r3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: or_tree_with_shifts_i32:
|
|
; CHECK-THUMB: @ %bb.0:
|
|
; CHECK-THUMB-NEXT: orrs r0, r2
|
|
; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #16
|
|
; CHECK-THUMB-NEXT: orrs r0, r3
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: or_tree_with_shifts_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: orrs r0, r2
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #16
|
|
; CHECK-ALIGN-NEXT: orrs r0, r3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: or_tree_with_shifts_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: orrs r0, r2
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #16
|
|
; CHECK-V6M-NEXT: orrs r0, r1
|
|
; CHECK-V6M-NEXT: orrs r0, r3
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = shl i32 %a, 16
|
|
%c.shifted = shl i32 %c, 16
|
|
%or.ab = or i32 %a.shifted, %b
|
|
%or.cd = or i32 %c.shifted, %d
|
|
%r = or i32 %or.ab, %or.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @xor_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-ARM-LABEL: xor_tree_with_shifts_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: eor r0, r0, r2
|
|
; CHECK-ARM-NEXT: eor r0, r1, r0, lsr #16
|
|
; CHECK-ARM-NEXT: eor r0, r0, r3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: xor_tree_with_shifts_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: eor r0, r0, r2
|
|
; CHECK-BE-NEXT: eor r0, r1, r0, lsr #16
|
|
; CHECK-BE-NEXT: eor r0, r0, r3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: xor_tree_with_shifts_i32:
|
|
; CHECK-THUMB: @ %bb.0:
|
|
; CHECK-THUMB-NEXT: eors r0, r2
|
|
; CHECK-THUMB-NEXT: eor.w r0, r1, r0, lsr #16
|
|
; CHECK-THUMB-NEXT: eors r0, r3
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: xor_tree_with_shifts_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: eors r0, r2
|
|
; CHECK-ALIGN-NEXT: eor.w r0, r1, r0, lsr #16
|
|
; CHECK-ALIGN-NEXT: eors r0, r3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: xor_tree_with_shifts_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: eors r0, r2
|
|
; CHECK-V6M-NEXT: lsrs r0, r0, #16
|
|
; CHECK-V6M-NEXT: eors r0, r1
|
|
; CHECK-V6M-NEXT: eors r0, r3
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = lshr i32 %a, 16
|
|
%c.shifted = lshr i32 %c, 16
|
|
%xor.ab = xor i32 %a.shifted, %b
|
|
%xor.cd = xor i32 %d, %c.shifted
|
|
%r = xor i32 %xor.ab, %xor.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @and_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-ARM-LABEL: and_tree_with_shifts_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: and r0, r0, r2
|
|
; CHECK-ARM-NEXT: and r0, r1, r0, asr #16
|
|
; CHECK-ARM-NEXT: and r0, r0, r3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: and_tree_with_shifts_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: and r0, r0, r2
|
|
; CHECK-BE-NEXT: and r0, r1, r0, asr #16
|
|
; CHECK-BE-NEXT: and r0, r0, r3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: and_tree_with_shifts_i32:
|
|
; CHECK-THUMB: @ %bb.0:
|
|
; CHECK-THUMB-NEXT: ands r0, r2
|
|
; CHECK-THUMB-NEXT: and.w r0, r1, r0, asr #16
|
|
; CHECK-THUMB-NEXT: ands r0, r3
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: and_tree_with_shifts_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: ands r0, r2
|
|
; CHECK-ALIGN-NEXT: and.w r0, r1, r0, asr #16
|
|
; CHECK-ALIGN-NEXT: ands r0, r3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: and_tree_with_shifts_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: ands r0, r2
|
|
; CHECK-V6M-NEXT: asrs r0, r0, #16
|
|
; CHECK-V6M-NEXT: ands r0, r1
|
|
; CHECK-V6M-NEXT: ands r0, r3
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = ashr i32 %a, 16
|
|
%c.shifted = ashr i32 %c, 16
|
|
%and.ab = and i32 %b, %a.shifted
|
|
%and.cd = and i32 %c.shifted, %d
|
|
%r = and i32 %and.ab, %and.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @logic_tree_with_shifts_var_i32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %s) {
|
|
; CHECK-ARM-LABEL: logic_tree_with_shifts_var_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: ldr r12, [sp]
|
|
; CHECK-ARM-NEXT: orr r0, r0, r2
|
|
; CHECK-ARM-NEXT: orr r0, r1, r0, lsl r12
|
|
; CHECK-ARM-NEXT: orr r0, r0, r3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: logic_tree_with_shifts_var_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: ldr r12, [sp]
|
|
; CHECK-BE-NEXT: orr r0, r0, r2
|
|
; CHECK-BE-NEXT: orr r0, r1, r0, lsl r12
|
|
; CHECK-BE-NEXT: orr r0, r0, r3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: logic_tree_with_shifts_var_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: orrs r0, r2
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp]
|
|
; CHECK-ALIGN-NEXT: lsls r0, r2
|
|
; CHECK-ALIGN-NEXT: orrs r0, r1
|
|
; CHECK-ALIGN-NEXT: orrs r0, r3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: logic_tree_with_shifts_var_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: orrs r0, r2
|
|
; CHECK-V6M-NEXT: ldr r2, [sp]
|
|
; CHECK-V6M-NEXT: lsls r0, r2
|
|
; CHECK-V6M-NEXT: orrs r0, r1
|
|
; CHECK-V6M-NEXT: orrs r0, r3
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = shl i32 %a, %s
|
|
%c.shifted = shl i32 %c, %s
|
|
%or.ab = or i32 %b, %a.shifted
|
|
%or.cd = or i32 %d, %c.shifted
|
|
%r = or i32 %or.ab, %or.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @logic_tree_with_mismatching_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-ARM-LABEL: logic_tree_with_mismatching_shifts_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: orr r2, r3, r2, lsl #16
|
|
; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #15
|
|
; CHECK-ARM-NEXT: orr r0, r0, r2
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: logic_tree_with_mismatching_shifts_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: orr r2, r3, r2, lsl #16
|
|
; CHECK-BE-NEXT: orr r0, r1, r0, lsl #15
|
|
; CHECK-BE-NEXT: orr r0, r0, r2
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: logic_tree_with_mismatching_shifts_i32:
|
|
; CHECK-THUMB: @ %bb.0:
|
|
; CHECK-THUMB-NEXT: orr.w r2, r3, r2, lsl #16
|
|
; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #15
|
|
; CHECK-THUMB-NEXT: orrs r0, r2
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: logic_tree_with_mismatching_shifts_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r3, r2, lsl #16
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #15
|
|
; CHECK-ALIGN-NEXT: orrs r0, r2
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: logic_tree_with_mismatching_shifts_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: lsls r2, r2, #16
|
|
; CHECK-V6M-NEXT: orrs r2, r3
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #15
|
|
; CHECK-V6M-NEXT: orrs r0, r1
|
|
; CHECK-V6M-NEXT: orrs r0, r2
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = shl i32 %a, 15
|
|
%c.shifted = shl i32 %c, 16
|
|
%or.ab = or i32 %a.shifted, %b
|
|
%or.cd = or i32 %c.shifted, %d
|
|
%r = or i32 %or.ab, %or.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @logic_tree_with_mismatching_shifts2_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
|
|
; CHECK-ARM-LABEL: logic_tree_with_mismatching_shifts2_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: orr r2, r3, r2, lsr #16
|
|
; CHECK-ARM-NEXT: orr r0, r1, r0, lsl #16
|
|
; CHECK-ARM-NEXT: orr r0, r0, r2
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: logic_tree_with_mismatching_shifts2_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: orr r2, r3, r2, lsr #16
|
|
; CHECK-BE-NEXT: orr r0, r1, r0, lsl #16
|
|
; CHECK-BE-NEXT: orr r0, r0, r2
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: logic_tree_with_mismatching_shifts2_i32:
|
|
; CHECK-THUMB: @ %bb.0:
|
|
; CHECK-THUMB-NEXT: orr.w r2, r3, r2, lsr #16
|
|
; CHECK-THUMB-NEXT: orr.w r0, r1, r0, lsl #16
|
|
; CHECK-THUMB-NEXT: orrs r0, r2
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: logic_tree_with_mismatching_shifts2_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r3, r2, lsr #16
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r1, r0, lsl #16
|
|
; CHECK-ALIGN-NEXT: orrs r0, r2
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: logic_tree_with_mismatching_shifts2_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: lsrs r2, r2, #16
|
|
; CHECK-V6M-NEXT: orrs r2, r3
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #16
|
|
; CHECK-V6M-NEXT: orrs r0, r1
|
|
; CHECK-V6M-NEXT: orrs r0, r2
|
|
; CHECK-V6M-NEXT: bx lr
|
|
%a.shifted = shl i32 %a, 16
|
|
%c.shifted = lshr i32 %c, 16
|
|
%or.ab = or i32 %a.shifted, %b
|
|
%or.cd = or i32 %c.shifted, %d
|
|
%r = or i32 %or.ab, %or.cd
|
|
ret i32 %r
|
|
}
|
|
|
|
define <4 x i32> @or_tree_with_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
|
|
; CHECK-ARM-LABEL: or_tree_with_shifts_vec_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: vorr q8, q0, q2
|
|
; CHECK-ARM-NEXT: vshl.i32 q8, q8, #16
|
|
; CHECK-ARM-NEXT: vorr q8, q8, q1
|
|
; CHECK-ARM-NEXT: vorr q0, q8, q3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: or_tree_with_shifts_vec_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: vrev64.32 q8, q2
|
|
; CHECK-BE-NEXT: vrev64.32 q9, q0
|
|
; CHECK-BE-NEXT: vorr q8, q9, q8
|
|
; CHECK-BE-NEXT: vrev64.32 q9, q1
|
|
; CHECK-BE-NEXT: vrev64.32 q10, q3
|
|
; CHECK-BE-NEXT: vshl.i32 q8, q8, #16
|
|
; CHECK-BE-NEXT: vorr q8, q8, q9
|
|
; CHECK-BE-NEXT: vorr q8, q8, q10
|
|
; CHECK-BE-NEXT: vrev64.32 q0, q8
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: or_tree_with_shifts_vec_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r12, r0
|
|
; CHECK-ALIGN-NEXT: ldr r0, [sp]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r0, r12, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr r0, [sp, #32]
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r12, r1
|
|
; CHECK-ALIGN-NEXT: ldr r1, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r1, r12, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr r1, [sp, #36]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #24]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r12, r2
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r2, r12, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp, #40]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #28]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r12, r3
|
|
; CHECK-ALIGN-NEXT: ldr r3, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, r3, r12, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr r3, [sp, #44]
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: or_tree_with_shifts_vec_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #24]
|
|
; CHECK-V6M-NEXT: orrs r4, r0
|
|
; CHECK-V6M-NEXT: lsls r0, r4, #16
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #8]
|
|
; CHECK-V6M-NEXT: orrs r4, r0
|
|
; CHECK-V6M-NEXT: ldr r0, [sp, #40]
|
|
; CHECK-V6M-NEXT: orrs r0, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #28]
|
|
; CHECK-V6M-NEXT: orrs r4, r1
|
|
; CHECK-V6M-NEXT: lsls r1, r4, #16
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #12]
|
|
; CHECK-V6M-NEXT: orrs r4, r1
|
|
; CHECK-V6M-NEXT: ldr r1, [sp, #44]
|
|
; CHECK-V6M-NEXT: orrs r1, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #32]
|
|
; CHECK-V6M-NEXT: orrs r4, r2
|
|
; CHECK-V6M-NEXT: lsls r2, r4, #16
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #16]
|
|
; CHECK-V6M-NEXT: orrs r4, r2
|
|
; CHECK-V6M-NEXT: ldr r2, [sp, #48]
|
|
; CHECK-V6M-NEXT: orrs r2, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #36]
|
|
; CHECK-V6M-NEXT: orrs r4, r3
|
|
; CHECK-V6M-NEXT: lsls r3, r4, #16
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #20]
|
|
; CHECK-V6M-NEXT: orrs r4, r3
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #52]
|
|
; CHECK-V6M-NEXT: orrs r3, r4
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
%a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>
|
|
%c.shifted = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
|
|
%or.ab = or <4 x i32> %a.shifted, %b
|
|
%or.cd = or <4 x i32> %c.shifted, %d
|
|
%r = or <4 x i32> %or.ab, %or.cd
|
|
ret <4 x i32> %r
|
|
}
|
|
|
|
define <4 x i32> @or_tree_with_mismatching_shifts_vec_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
|
|
; CHECK-ARM-LABEL: or_tree_with_mismatching_shifts_vec_i32:
|
|
; CHECK-ARM: @ %bb.0:
|
|
; CHECK-ARM-NEXT: vshl.i32 q8, q2, #17
|
|
; CHECK-ARM-NEXT: vshl.i32 q9, q0, #16
|
|
; CHECK-ARM-NEXT: vorr q8, q8, q3
|
|
; CHECK-ARM-NEXT: vorr q9, q9, q1
|
|
; CHECK-ARM-NEXT: vorr q0, q9, q8
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: or_tree_with_mismatching_shifts_vec_i32:
|
|
; CHECK-BE: @ %bb.0:
|
|
; CHECK-BE-NEXT: vrev64.32 q8, q2
|
|
; CHECK-BE-NEXT: vrev64.32 q9, q0
|
|
; CHECK-BE-NEXT: vshl.i32 q8, q8, #17
|
|
; CHECK-BE-NEXT: vrev64.32 q10, q3
|
|
; CHECK-BE-NEXT: vshl.i32 q9, q9, #16
|
|
; CHECK-BE-NEXT: vrev64.32 q11, q1
|
|
; CHECK-BE-NEXT: vorr q8, q8, q10
|
|
; CHECK-BE-NEXT: vorr q9, q9, q11
|
|
; CHECK-BE-NEXT: vorr q8, q9, q8
|
|
; CHECK-BE-NEXT: vrev64.32 q0, q8
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: or_tree_with_mismatching_shifts_vec_i32:
|
|
; CHECK-ALIGN: @ %bb.0:
|
|
; CHECK-ALIGN-NEXT: push {r7, lr}
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #24]
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #40]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, lr, r12, lsl #17
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r0, lr, r0, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #44]
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #28]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, lr, r12, lsl #17
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, lr, r1, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #48]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #32]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, lr, r12, lsl #17
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, lr, r2, lsl #16
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #52]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #36]
|
|
; CHECK-ALIGN-NEXT: orr.w r12, lr, r12, lsl #17
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: orr.w r3, lr, r3, lsl #16
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12
|
|
; CHECK-ALIGN-NEXT: pop {r7, pc}
|
|
;
|
|
; CHECK-V6M-LABEL: or_tree_with_mismatching_shifts_vec_i32:
|
|
; CHECK-V6M: @ %bb.0:
|
|
; CHECK-V6M-NEXT: push {r4, r5, r7, lr}
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #32]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #17
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #48]
|
|
; CHECK-V6M-NEXT: orrs r5, r4
|
|
; CHECK-V6M-NEXT: lsls r4, r0, #16
|
|
; CHECK-V6M-NEXT: ldr r0, [sp, #16]
|
|
; CHECK-V6M-NEXT: orrs r0, r4
|
|
; CHECK-V6M-NEXT: orrs r0, r5
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #36]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #17
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #52]
|
|
; CHECK-V6M-NEXT: orrs r5, r4
|
|
; CHECK-V6M-NEXT: lsls r4, r1, #16
|
|
; CHECK-V6M-NEXT: ldr r1, [sp, #20]
|
|
; CHECK-V6M-NEXT: orrs r1, r4
|
|
; CHECK-V6M-NEXT: orrs r1, r5
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #40]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #17
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #56]
|
|
; CHECK-V6M-NEXT: orrs r5, r4
|
|
; CHECK-V6M-NEXT: lsls r4, r2, #16
|
|
; CHECK-V6M-NEXT: ldr r2, [sp, #24]
|
|
; CHECK-V6M-NEXT: orrs r2, r4
|
|
; CHECK-V6M-NEXT: orrs r2, r5
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #44]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #17
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #60]
|
|
; CHECK-V6M-NEXT: orrs r5, r4
|
|
; CHECK-V6M-NEXT: lsls r4, r3, #16
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #28]
|
|
; CHECK-V6M-NEXT: orrs r3, r4
|
|
; CHECK-V6M-NEXT: orrs r3, r5
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r7, pc}
|
|
%a.shifted = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>
|
|
%c.shifted = shl <4 x i32> %c, <i32 17, i32 17, i32 17, i32 17>
|
|
%or.ab = or <4 x i32> %a.shifted, %b
|
|
%or.cd = or <4 x i32> %c.shifted, %d
|
|
%r = or <4 x i32> %or.ab, %or.cd
|
|
ret <4 x i32> %r
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_shift15_and510(ptr nocapture %p) {
|
|
; CHECK-ARM-LABEL: test_shift15_and510:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-ARM-NEXT: lsl r0, r0, #1
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift15_and510:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-BE-NEXT: lsl r0, r0, #1
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_shift15_and510:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-THUMB-NEXT: lsls r0, r0, #1
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_shift15_and510:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-ALIGN-NEXT: lsls r0, r0, #1
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift15_and510:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r0, [r0, #2]
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #1
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%load = load i32, ptr %p, align 4
|
|
%lshr = lshr i32 %load, 15
|
|
%and = and i32 %lshr, 510
|
|
ret i32 %and
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_shift22_and1020(ptr nocapture %p) {
|
|
; CHECK-ARM-LABEL: test_shift22_and1020:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrb r0, [r0, #3]
|
|
; CHECK-ARM-NEXT: lsl r0, r0, #2
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_shift22_and1020:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: lsl r0, r0, #2
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_shift22_and1020:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrb r0, [r0, #3]
|
|
; CHECK-THUMB-NEXT: lsls r0, r0, #2
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_shift22_and1020:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrb r0, [r0, #3]
|
|
; CHECK-ALIGN-NEXT: lsls r0, r0, #2
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_shift22_and1020:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r0, [r0, #3]
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #2
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%load = load i32, ptr %p, align 4
|
|
%lshr = lshr i32 %load, 22
|
|
%and = and i32 %lshr, 1020
|
|
ret i32 %and
|
|
}
|
|
|
|
define arm_aapcscc i32 @test_zext_shift5_and2040(ptr nocapture %p) {
|
|
; CHECK-ARM-LABEL: test_zext_shift5_and2040:
|
|
; CHECK-ARM: @ %bb.0: @ %entry
|
|
; CHECK-ARM-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-ARM-NEXT: lsl r0, r0, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: test_zext_shift5_and2040:
|
|
; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: ldrb r0, [r0]
|
|
; CHECK-BE-NEXT: lsl r0, r0, #3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-THUMB-LABEL: test_zext_shift5_and2040:
|
|
; CHECK-THUMB: @ %bb.0: @ %entry
|
|
; CHECK-THUMB-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-THUMB-NEXT: lsls r0, r0, #3
|
|
; CHECK-THUMB-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: test_zext_shift5_and2040:
|
|
; CHECK-ALIGN: @ %bb.0: @ %entry
|
|
; CHECK-ALIGN-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-ALIGN-NEXT: lsls r0, r0, #3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: test_zext_shift5_and2040:
|
|
; CHECK-V6M: @ %bb.0: @ %entry
|
|
; CHECK-V6M-NEXT: ldrb r0, [r0, #1]
|
|
; CHECK-V6M-NEXT: lsls r0, r0, #3
|
|
; CHECK-V6M-NEXT: bx lr
|
|
entry:
|
|
%load = load i16, ptr %p, align 2
|
|
%zext = zext i16 %load to i32
|
|
%lshr = lshr i32 %zext, 5
|
|
%and = and i32 %lshr, 2040
|
|
ret i32 %and
|
|
}
|
|
|
|
define <8 x i8> @lshr_into_vsri_i8(<8 x i8> %a, <8 x i8> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_i8:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.8 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_i8:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.8 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.8 d17, d0
|
|
; CHECK-BE-NEXT: vsri.8 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.8 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_i8:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #52]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #7]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #48]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #6]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #44]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #5]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #40]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #4]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #36]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #3]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #32]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #2]
|
|
; CHECK-ALIGN-NEXT: and r1, r3, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r3, [sp, #28]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #1]
|
|
; CHECK-ALIGN-NEXT: and r1, r2, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r2, [sp, #24]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_i8:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r7, lr}
|
|
; CHECK-V6M-NEXT: add r1, sp, #36
|
|
; CHECK-V6M-NEXT: ldrb r4, [r1]
|
|
; CHECK-V6M-NEXT: movs r1, #224
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #68
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #7]
|
|
; CHECK-V6M-NEXT: add r4, sp, #32
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #64
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #6]
|
|
; CHECK-V6M-NEXT: add r4, sp, #28
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #60
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #5]
|
|
; CHECK-V6M-NEXT: add r4, sp, #24
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #56
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #4]
|
|
; CHECK-V6M-NEXT: add r4, sp, #20
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #52
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #3]
|
|
; CHECK-V6M-NEXT: add r4, sp, #16
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #48
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #2]
|
|
; CHECK-V6M-NEXT: ands r3, r1
|
|
; CHECK-V6M-NEXT: add r4, sp, #44
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: lsrs r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: strb r3, [r0, #1]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: add r1, sp, #40
|
|
; CHECK-V6M-NEXT: ldrb r1, [r1]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #3
|
|
; CHECK-V6M-NEXT: adds r1, r1, r2
|
|
; CHECK-V6M-NEXT: strb r1, [r0]
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r7, pc}
|
|
bb1:
|
|
%0 = and <8 x i8> %a, splat (i8 -32)
|
|
%1 = lshr <8 x i8> %b, splat (i8 3)
|
|
%2 = or disjoint <8 x i8> %1, %0
|
|
ret <8 x i8> %2
|
|
}
|
|
|
|
define <8 x i8> @shl_into_vsli_i8(<8 x i8> %a, <8 x i8> %b) {
|
|
; CHECK-ARM-LABEL: shl_into_vsli_i8:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsli.8 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: shl_into_vsli_i8:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.8 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.8 d17, d0
|
|
; CHECK-BE-NEXT: vsli.8 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.8 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: shl_into_vsli_i8:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #52]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #7]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #48]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #6]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #44]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #5]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #40]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #4]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #36]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #3]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #32]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #2]
|
|
; CHECK-ALIGN-NEXT: and r1, r3, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r3, [sp, #28]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #1]
|
|
; CHECK-ALIGN-NEXT: and r1, r2, #7
|
|
; CHECK-ALIGN-NEXT: ldrb.w r2, [sp, #24]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsl #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: shl_into_vsli_i8:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r1, #7
|
|
; CHECK-V6M-NEXT: ands r3, r1
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #36]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: strb r3, [r0, #1]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #32]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0]
|
|
; CHECK-V6M-NEXT: add r2, sp, #28
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #60]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0, #7]
|
|
; CHECK-V6M-NEXT: add r2, sp, #24
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #56]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0, #6]
|
|
; CHECK-V6M-NEXT: add r2, sp, #20
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #52]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0, #5]
|
|
; CHECK-V6M-NEXT: add r2, sp, #16
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #48]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0, #4]
|
|
; CHECK-V6M-NEXT: add r2, sp, #12
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #44]
|
|
; CHECK-V6M-NEXT: lsls r3, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r3, r2
|
|
; CHECK-V6M-NEXT: strb r2, [r0, #3]
|
|
; CHECK-V6M-NEXT: add r2, sp, #8
|
|
; CHECK-V6M-NEXT: ldrb r2, [r2]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: ldr r1, [sp, #40]
|
|
; CHECK-V6M-NEXT: lsls r1, r1, #3
|
|
; CHECK-V6M-NEXT: adds r1, r1, r2
|
|
; CHECK-V6M-NEXT: strb r1, [r0, #2]
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <8 x i8> %a, splat (i8 7)
|
|
%1 = shl <8 x i8> %b, splat (i8 3)
|
|
%2 = or disjoint <8 x i8> %1, %0
|
|
ret <8 x i8> %2
|
|
}
|
|
|
|
define <4 x i16> @lshr_into_vsri_i16(<4 x i16> %a, <4 x i16> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_i16:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.16 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_i16:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.16 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.16 d17, d0
|
|
; CHECK-BE-NEXT: vsri.16 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.16 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_i16:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: movw r12, #8191
|
|
; CHECK-ALIGN-NEXT: bfc r1, #0, #13
|
|
; CHECK-ALIGN-NEXT: bic.w r12, r0, r12
|
|
; CHECK-ALIGN-NEXT: ldrh.w r0, [sp]
|
|
; CHECK-ALIGN-NEXT: bfc r2, #0, #13
|
|
; CHECK-ALIGN-NEXT: bfc r3, #0, #13
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r12, r0, lsr #3
|
|
; CHECK-ALIGN-NEXT: ldrh.w r12, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r12, lsr #3
|
|
; CHECK-ALIGN-NEXT: ldrh.w r12, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12, lsr #3
|
|
; CHECK-ALIGN-NEXT: ldrh.w r12, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12, lsr #3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_i16:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r7, lr}
|
|
; CHECK-V6M-NEXT: ldr r4, .LCPI41_0
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: add r5, sp, #16
|
|
; CHECK-V6M-NEXT: ldrh r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r0, r5, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: add r5, sp, #20
|
|
; CHECK-V6M-NEXT: ldrh r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r1, r5, r1
|
|
; CHECK-V6M-NEXT: ands r2, r4
|
|
; CHECK-V6M-NEXT: add r5, sp, #24
|
|
; CHECK-V6M-NEXT: ldrh r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r2, r5, r2
|
|
; CHECK-V6M-NEXT: ands r3, r4
|
|
; CHECK-V6M-NEXT: add r4, sp, #28
|
|
; CHECK-V6M-NEXT: ldrh r4, [r4]
|
|
; CHECK-V6M-NEXT: lsrs r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r7, pc}
|
|
; CHECK-V6M-NEXT: .p2align 2
|
|
; CHECK-V6M-NEXT: @ %bb.1:
|
|
; CHECK-V6M-NEXT: .LCPI41_0:
|
|
; CHECK-V6M-NEXT: .long 4294959104 @ 0xffffe000
|
|
bb1:
|
|
%0 = and <4 x i16> %a, splat (i16 -8192)
|
|
%1 = lshr <4 x i16> %b, splat (i16 3)
|
|
%2 = or disjoint <4 x i16> %1, %0
|
|
ret <4 x i16> %2
|
|
}
|
|
|
|
define <4 x i16> @shl_into_vsli_i16(<4 x i16> %a, <4 x i16> %b) {
|
|
; CHECK-ARM-LABEL: shl_into_vsli_i16:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsli.16 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: shl_into_vsli_i16:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.16 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.16 d17, d0
|
|
; CHECK-BE-NEXT: vsli.16 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.16 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: shl_into_vsli_i16:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: and r12, r0, #7
|
|
; CHECK-ALIGN-NEXT: ldrh.w r0, [sp]
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r12, r0, lsl #3
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #7
|
|
; CHECK-ALIGN-NEXT: ldrh.w r1, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: and r12, r2, #7
|
|
; CHECK-ALIGN-NEXT: ldrh.w r2, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r12, r2, lsl #3
|
|
; CHECK-ALIGN-NEXT: and r12, r3, #7
|
|
; CHECK-ALIGN-NEXT: ldrh.w r3, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r12, r3, lsl #3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: shl_into_vsli_i16:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r7, lr}
|
|
; CHECK-V6M-NEXT: movs r4, #7
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #16]
|
|
; CHECK-V6M-NEXT: lsls r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r0, r5, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #20]
|
|
; CHECK-V6M-NEXT: lsls r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r1, r5, r1
|
|
; CHECK-V6M-NEXT: ands r2, r4
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #24]
|
|
; CHECK-V6M-NEXT: lsls r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r2, r5, r2
|
|
; CHECK-V6M-NEXT: ands r3, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #28]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r7, pc}
|
|
bb1:
|
|
%0 = and <4 x i16> %a, splat (i16 7)
|
|
%1 = shl <4 x i16> %b, splat (i16 3)
|
|
%2 = or disjoint <4 x i16> %1, %0
|
|
ret <4 x i16> %2
|
|
}
|
|
|
|
define <2 x i32> @lshr_into_vsri_i32(<2 x i32> %a, <2 x i32> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_i32:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.32 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_i32:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.32 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.32 d17, d0
|
|
; CHECK-BE-NEXT: vsri.32 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.32 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_i32:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #-536870912
|
|
; CHECK-ALIGN-NEXT: and r1, r1, #-536870912
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsr #3
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsr #3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_i32:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r4, #7
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #29
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: lsrs r2, r2, #3
|
|
; CHECK-V6M-NEXT: adds r0, r2, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: lsrs r2, r3, #3
|
|
; CHECK-V6M-NEXT: adds r1, r2, r1
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <2 x i32> %a, splat (i32 -536870912)
|
|
%1 = lshr <2 x i32> %b, splat (i32 3)
|
|
%2 = or disjoint <2 x i32> %1, %0
|
|
ret <2 x i32> %2
|
|
}
|
|
|
|
define <2 x i32> @shl_into_vsli_i32(<2 x i32> %a, <2 x i32> %b) {
|
|
; CHECK-ARM-LABEL: shl_into_vsli_i32:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsli.32 d0, d1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: shl_into_vsli_i32:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.32 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.32 d17, d0
|
|
; CHECK-BE-NEXT: vsli.32 d17, d16, #3
|
|
; CHECK-BE-NEXT: vrev64.32 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: shl_into_vsli_i32:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #7
|
|
; CHECK-ALIGN-NEXT: and r1, r1, #7
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsl #3
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsl #3
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: shl_into_vsli_i32:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r4, #7
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: lsls r2, r2, #3
|
|
; CHECK-V6M-NEXT: adds r0, r2, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: lsls r2, r3, #3
|
|
; CHECK-V6M-NEXT: adds r1, r2, r1
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <2 x i32> %a, splat (i32 7)
|
|
%1 = shl <2 x i32> %b, splat (i32 3)
|
|
%2 = or disjoint <2 x i32> %1, %0
|
|
ret <2 x i32> %2
|
|
}
|
|
|
|
define <2 x i32> @lshr_into_vsri_shift1_i32(<2 x i32> %a, <2 x i32> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_shift1_i32:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.32 d0, d1, #1
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_shift1_i32:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.32 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.32 d17, d0
|
|
; CHECK-BE-NEXT: vsri.32 d17, d16, #1
|
|
; CHECK-BE-NEXT: vrev64.32 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_shift1_i32:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #-2147483648
|
|
; CHECK-ALIGN-NEXT: and r1, r1, #-2147483648
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsr #1
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsr #1
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_shift1_i32:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r4, #1
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #31
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: lsrs r2, r2, #1
|
|
; CHECK-V6M-NEXT: adds r0, r2, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: lsrs r2, r3, #1
|
|
; CHECK-V6M-NEXT: adds r1, r2, r1
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <2 x i32> %a, splat (i32 -2147483648)
|
|
%1 = lshr <2 x i32> %b, splat (i32 1)
|
|
%2 = or disjoint <2 x i32> %1, %0
|
|
ret <2 x i32> %2
|
|
}
|
|
|
|
define <2 x i32> @shl_into_vsli_shift1(<2 x i32> %a, <2 x i32> %b) {
|
|
; CHECK-ARM-LABEL: shl_into_vsli_shift1:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsli.32 d0, d1, #1
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: shl_into_vsli_shift1:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.32 d16, d1
|
|
; CHECK-BE-NEXT: vrev64.32 d17, d0
|
|
; CHECK-BE-NEXT: vsli.32 d17, d16, #1
|
|
; CHECK-BE-NEXT: vrev64.32 d0, d17
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: shl_into_vsli_shift1:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #1
|
|
; CHECK-ALIGN-NEXT: and r1, r1, #1
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsl #1
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsl #1
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: shl_into_vsli_shift1:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r4, #1
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: lsls r2, r2, #1
|
|
; CHECK-V6M-NEXT: adds r0, r2, r0
|
|
; CHECK-V6M-NEXT: ands r1, r4
|
|
; CHECK-V6M-NEXT: lsls r2, r3, #1
|
|
; CHECK-V6M-NEXT: adds r1, r2, r1
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <2 x i32> %a, splat (i32 1)
|
|
%1 = shl <2 x i32> %b, splat (i32 1)
|
|
%2 = or disjoint <2 x i32> %1, %0
|
|
ret <2 x i32> %2
|
|
}
|
|
|
|
define <2 x i64> @lshr_into_vsri_i64(<2 x i64> %a, <2 x i64> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_i64:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.64 q0, q1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_i64:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vsri.64 q0, q1, #3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_i64:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: ldr r0, [sp]
|
|
; CHECK-ALIGN-NEXT: and r1, r1, #-536870912
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: and r3, r3, #-536870912
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: lsrs r0, r0, #3
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r2, lsl #29
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsr #3
|
|
; CHECK-ALIGN-NEXT: ldr r2, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12, lsr #3
|
|
; CHECK-ALIGN-NEXT: lsrs r2, r2, #3
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12, lsl #29
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_i64:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r6, lr}
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #20]
|
|
; CHECK-V6M-NEXT: lsls r0, r4, #29
|
|
; CHECK-V6M-NEXT: ldr r2, [sp, #16]
|
|
; CHECK-V6M-NEXT: lsrs r2, r2, #3
|
|
; CHECK-V6M-NEXT: adds r0, r2, r0
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #28]
|
|
; CHECK-V6M-NEXT: lsls r2, r5, #29
|
|
; CHECK-V6M-NEXT: ldr r6, [sp, #24]
|
|
; CHECK-V6M-NEXT: lsrs r6, r6, #3
|
|
; CHECK-V6M-NEXT: adds r2, r6, r2
|
|
; CHECK-V6M-NEXT: movs r6, #7
|
|
; CHECK-V6M-NEXT: lsls r6, r6, #29
|
|
; CHECK-V6M-NEXT: ands r1, r6
|
|
; CHECK-V6M-NEXT: lsrs r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r1, r4, r1
|
|
; CHECK-V6M-NEXT: ands r3, r6
|
|
; CHECK-V6M-NEXT: lsrs r4, r5, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r6, pc}
|
|
bb1:
|
|
%0 = and <2 x i64> %a, splat (i64 -2305843009213693952)
|
|
%1 = lshr <2 x i64> %b, splat (i64 3)
|
|
%2 = or disjoint <2 x i64> %1, %0
|
|
ret <2 x i64> %2
|
|
}
|
|
|
|
define <2 x i64> @shl_into_vsli_i64(<2 x i64> %a, <2 x i64> %b) {
|
|
; CHECK-ARM-LABEL: shl_into_vsli_i64:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsli.64 q0, q1, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: shl_into_vsli_i64:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vsli.64 q0, q1, #3
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: shl_into_vsli_i64:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: ldr r3, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #7
|
|
; CHECK-ALIGN-NEXT: ldr r1, [sp]
|
|
; CHECK-ALIGN-NEXT: and r2, r2, #7
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: lsls r3, r3, #3
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r1, lsl #3
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r3, r1, lsr #29
|
|
; CHECK-ALIGN-NEXT: ldr r3, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12, lsl #3
|
|
; CHECK-ALIGN-NEXT: lsls r3, r3, #3
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, r12, lsr #29
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: shl_into_vsli_i64:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, lr}
|
|
; CHECK-V6M-NEXT: movs r3, #7
|
|
; CHECK-V6M-NEXT: ands r0, r3
|
|
; CHECK-V6M-NEXT: ldr r1, [sp, #8]
|
|
; CHECK-V6M-NEXT: lsls r4, r1, #3
|
|
; CHECK-V6M-NEXT: adds r0, r4, r0
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #29
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #12]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r1, r4, r1
|
|
; CHECK-V6M-NEXT: ands r2, r3
|
|
; CHECK-V6M-NEXT: ldr r3, [sp, #16]
|
|
; CHECK-V6M-NEXT: lsls r4, r3, #3
|
|
; CHECK-V6M-NEXT: adds r2, r4, r2
|
|
; CHECK-V6M-NEXT: lsrs r3, r3, #29
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #20]
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: pop {r4, pc}
|
|
bb1:
|
|
%0 = and <2 x i64> %a, splat (i64 7)
|
|
%1 = shl <2 x i64> %b, splat (i64 3)
|
|
%2 = or disjoint <2 x i64> %1, %0
|
|
ret <2 x i64> %2
|
|
}
|
|
|
|
define <2 x i64> @lshr_into_vsri_shift1_i64(<2 x i64> %a, <2 x i64> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_shift1_i64:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: adr r0, .LCPI49_0
|
|
; CHECK-ARM-NEXT: vshr.u64 q9, q1, #1
|
|
; CHECK-ARM-NEXT: vld1.64 {d16, d17}, [r0:128]
|
|
; CHECK-ARM-NEXT: vand q8, q0, q8
|
|
; CHECK-ARM-NEXT: vorr q0, q9, q8
|
|
; CHECK-ARM-NEXT: bx lr
|
|
; CHECK-ARM-NEXT: .p2align 4
|
|
; CHECK-ARM-NEXT: @ %bb.1:
|
|
; CHECK-ARM-NEXT: .LCPI49_0:
|
|
; CHECK-ARM-NEXT: .long 2147483648 @ 0x80000000
|
|
; CHECK-ARM-NEXT: .long 4294967295 @ 0xffffffff
|
|
; CHECK-ARM-NEXT: .long 2147483648 @ 0x80000000
|
|
; CHECK-ARM-NEXT: .long 4294967295 @ 0xffffffff
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_shift1_i64:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: adr r0, .LCPI49_0
|
|
; CHECK-BE-NEXT: vshr.u64 q9, q1, #1
|
|
; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0:128]
|
|
; CHECK-BE-NEXT: vand q8, q0, q8
|
|
; CHECK-BE-NEXT: vorr q0, q9, q8
|
|
; CHECK-BE-NEXT: bx lr
|
|
; CHECK-BE-NEXT: .p2align 4
|
|
; CHECK-BE-NEXT: @ %bb.1:
|
|
; CHECK-BE-NEXT: .LCPI49_0:
|
|
; CHECK-BE-NEXT: .long 4294967295 @ 0xffffffff
|
|
; CHECK-BE-NEXT: .long 2147483648 @ 0x80000000
|
|
; CHECK-BE-NEXT: .long 4294967295 @ 0xffffffff
|
|
; CHECK-BE-NEXT: .long 2147483648 @ 0x80000000
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_shift1_i64:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: push {r7, lr}
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: and r0, r0, #-2147483648
|
|
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: and r2, r2, #-2147483648
|
|
; CHECK-ALIGN-NEXT: lsrs.w r12, r12, #1
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: rrx r12, r12
|
|
; CHECK-ALIGN-NEXT: orr.w r0, r0, r12
|
|
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: lsrs.w lr, lr, #1
|
|
; CHECK-ALIGN-NEXT: orr.w r3, r3, lr
|
|
; CHECK-ALIGN-NEXT: rrx r12, r12
|
|
; CHECK-ALIGN-NEXT: orr.w r2, r2, r12
|
|
; CHECK-ALIGN-NEXT: pop {r7, pc}
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_shift1_i64:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r6, r7, lr}
|
|
; CHECK-V6M-NEXT: sub sp, #4
|
|
; CHECK-V6M-NEXT: movs r4, #1
|
|
; CHECK-V6M-NEXT: lsls r4, r4, #31
|
|
; CHECK-V6M-NEXT: ands r0, r4
|
|
; CHECK-V6M-NEXT: ldr r5, [sp, #28]
|
|
; CHECK-V6M-NEXT: lsls r6, r5, #31
|
|
; CHECK-V6M-NEXT: ldr r7, [sp, #24]
|
|
; CHECK-V6M-NEXT: lsrs r7, r7, #1
|
|
; CHECK-V6M-NEXT: adds r6, r7, r6
|
|
; CHECK-V6M-NEXT: orrs r0, r6
|
|
; CHECK-V6M-NEXT: ands r2, r4
|
|
; CHECK-V6M-NEXT: ldr r4, [sp, #36]
|
|
; CHECK-V6M-NEXT: lsls r6, r4, #31
|
|
; CHECK-V6M-NEXT: ldr r7, [sp, #32]
|
|
; CHECK-V6M-NEXT: lsrs r7, r7, #1
|
|
; CHECK-V6M-NEXT: adds r6, r7, r6
|
|
; CHECK-V6M-NEXT: orrs r2, r6
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #1
|
|
; CHECK-V6M-NEXT: orrs r1, r5
|
|
; CHECK-V6M-NEXT: lsrs r4, r4, #1
|
|
; CHECK-V6M-NEXT: orrs r3, r4
|
|
; CHECK-V6M-NEXT: add sp, #4
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r6, r7, pc}
|
|
bb1:
|
|
%0 = and <2 x i64> %a, splat (i64 -2147483648)
|
|
%1 = lshr <2 x i64> %b, splat (i64 1)
|
|
%2 = or disjoint <2 x i64> %1, %0
|
|
ret <2 x i64> %2
|
|
}
|
|
|
|
define <32 x i8> @lshr_into_vsri_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
|
; CHECK-ARM-LABEL: lshr_into_vsri_v32i8:
|
|
; CHECK-ARM: @ %bb.0: @ %bb1
|
|
; CHECK-ARM-NEXT: vsri.8 q0, q2, #3
|
|
; CHECK-ARM-NEXT: vsri.8 q1, q3, #3
|
|
; CHECK-ARM-NEXT: bx lr
|
|
;
|
|
; CHECK-BE-LABEL: lshr_into_vsri_v32i8:
|
|
; CHECK-BE: @ %bb.0: @ %bb1
|
|
; CHECK-BE-NEXT: vrev64.8 q8, q2
|
|
; CHECK-BE-NEXT: vrev64.8 q9, q0
|
|
; CHECK-BE-NEXT: vrev64.8 q10, q3
|
|
; CHECK-BE-NEXT: vsri.8 q9, q8, #3
|
|
; CHECK-BE-NEXT: vrev64.8 q11, q1
|
|
; CHECK-BE-NEXT: vsri.8 q11, q10, #3
|
|
; CHECK-BE-NEXT: vrev64.8 q0, q9
|
|
; CHECK-BE-NEXT: vrev64.8 q1, q11
|
|
; CHECK-BE-NEXT: bx lr
|
|
;
|
|
; CHECK-ALIGN-LABEL: lshr_into_vsri_v32i8:
|
|
; CHECK-ALIGN: @ %bb.0: @ %bb1
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #116]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #244]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #31]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #112]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #240]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #30]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #108]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #236]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #29]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #104]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #232]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #28]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #100]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #228]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #27]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #96]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #224]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #26]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #92]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #220]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #25]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #88]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #216]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #24]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #84]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #212]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #23]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #80]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #208]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #22]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #76]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #204]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #21]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #72]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #200]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #20]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #68]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #196]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #19]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #64]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #192]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #18]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #60]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #188]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #17]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #56]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #184]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #16]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #52]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #180]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #15]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #48]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #176]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #14]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #44]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #172]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #13]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #40]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #168]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #12]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #36]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #164]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #11]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #32]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #160]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #10]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #28]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #156]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #9]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #24]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #152]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #8]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #20]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #148]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #7]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #16]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #144]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #6]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #12]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #140]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #5]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #8]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #136]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #4]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #4]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #132]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #3]
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp]
|
|
; CHECK-ALIGN-NEXT: and r12, r1, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r1, [sp, #128]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r12, r1, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #2]
|
|
; CHECK-ALIGN-NEXT: and r1, r3, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r3, [sp, #124]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r3, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0, #1]
|
|
; CHECK-ALIGN-NEXT: and r1, r2, #224
|
|
; CHECK-ALIGN-NEXT: ldrb.w r2, [sp, #120]
|
|
; CHECK-ALIGN-NEXT: orr.w r1, r1, r2, lsr #3
|
|
; CHECK-ALIGN-NEXT: strb r1, [r0]
|
|
; CHECK-ALIGN-NEXT: bx lr
|
|
;
|
|
; CHECK-V6M-LABEL: lshr_into_vsri_v32i8:
|
|
; CHECK-V6M: @ %bb.0: @ %bb1
|
|
; CHECK-V6M-NEXT: push {r4, r5, r7, lr}
|
|
; CHECK-V6M-NEXT: add r1, sp, #132
|
|
; CHECK-V6M-NEXT: ldrb r4, [r1]
|
|
; CHECK-V6M-NEXT: movs r1, #224
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #260
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #31]
|
|
; CHECK-V6M-NEXT: add r4, sp, #128
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #256
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #30]
|
|
; CHECK-V6M-NEXT: add r4, sp, #124
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #252
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #29]
|
|
; CHECK-V6M-NEXT: add r4, sp, #120
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #248
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #28]
|
|
; CHECK-V6M-NEXT: add r4, sp, #116
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #244
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #27]
|
|
; CHECK-V6M-NEXT: add r4, sp, #112
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #240
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #26]
|
|
; CHECK-V6M-NEXT: add r4, sp, #108
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #236
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #25]
|
|
; CHECK-V6M-NEXT: add r4, sp, #104
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #232
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #24]
|
|
; CHECK-V6M-NEXT: add r4, sp, #100
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #228
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #23]
|
|
; CHECK-V6M-NEXT: add r4, sp, #96
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #224
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #22]
|
|
; CHECK-V6M-NEXT: add r4, sp, #92
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #220
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #21]
|
|
; CHECK-V6M-NEXT: add r4, sp, #88
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #216
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #20]
|
|
; CHECK-V6M-NEXT: add r4, sp, #84
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #212
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #19]
|
|
; CHECK-V6M-NEXT: add r4, sp, #80
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #208
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #18]
|
|
; CHECK-V6M-NEXT: add r4, sp, #76
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #204
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #17]
|
|
; CHECK-V6M-NEXT: add r4, sp, #72
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #200
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #16]
|
|
; CHECK-V6M-NEXT: add r4, sp, #68
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #196
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #15]
|
|
; CHECK-V6M-NEXT: add r4, sp, #64
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #192
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #14]
|
|
; CHECK-V6M-NEXT: add r4, sp, #60
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #188
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #13]
|
|
; CHECK-V6M-NEXT: add r4, sp, #56
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #184
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #12]
|
|
; CHECK-V6M-NEXT: add r4, sp, #52
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #180
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #11]
|
|
; CHECK-V6M-NEXT: add r4, sp, #48
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #176
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #10]
|
|
; CHECK-V6M-NEXT: add r4, sp, #44
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #172
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #9]
|
|
; CHECK-V6M-NEXT: add r4, sp, #40
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #168
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #8]
|
|
; CHECK-V6M-NEXT: add r4, sp, #36
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #164
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #7]
|
|
; CHECK-V6M-NEXT: add r4, sp, #32
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #160
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #6]
|
|
; CHECK-V6M-NEXT: add r4, sp, #28
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #156
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #5]
|
|
; CHECK-V6M-NEXT: add r4, sp, #24
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #152
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #4]
|
|
; CHECK-V6M-NEXT: add r4, sp, #20
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #148
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #3]
|
|
; CHECK-V6M-NEXT: add r4, sp, #16
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: ands r4, r1
|
|
; CHECK-V6M-NEXT: add r5, sp, #144
|
|
; CHECK-V6M-NEXT: ldrb r5, [r5]
|
|
; CHECK-V6M-NEXT: lsrs r5, r5, #3
|
|
; CHECK-V6M-NEXT: adds r4, r5, r4
|
|
; CHECK-V6M-NEXT: strb r4, [r0, #2]
|
|
; CHECK-V6M-NEXT: ands r3, r1
|
|
; CHECK-V6M-NEXT: add r4, sp, #140
|
|
; CHECK-V6M-NEXT: ldrb r4, [r4]
|
|
; CHECK-V6M-NEXT: lsrs r4, r4, #3
|
|
; CHECK-V6M-NEXT: adds r3, r4, r3
|
|
; CHECK-V6M-NEXT: strb r3, [r0, #1]
|
|
; CHECK-V6M-NEXT: ands r2, r1
|
|
; CHECK-V6M-NEXT: add r1, sp, #136
|
|
; CHECK-V6M-NEXT: ldrb r1, [r1]
|
|
; CHECK-V6M-NEXT: lsrs r1, r1, #3
|
|
; CHECK-V6M-NEXT: adds r1, r1, r2
|
|
; CHECK-V6M-NEXT: strb r1, [r0]
|
|
; CHECK-V6M-NEXT: pop {r4, r5, r7, pc}
|
|
bb1:
|
|
%0 = and <32 x i8> %a, splat (i8 -32)
|
|
%1 = lshr <32 x i8> %b, splat (i8 3)
|
|
%2 = or disjoint <32 x i8> %1, %0
|
|
ret <32 x i8> %2
|
|
}
|