5012b76ae2
If a Or is detected by findPointerConstIncrement but not by getPointerConstIncrement it could use an invalid increment for the offset. Protect against cases where getPointerConstIncrement cannot return a valid offset. Fixes #185677
214 lines
7.9 KiB
LLVM
214 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
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%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> }
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%struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
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;Check the alignment value. Max for this instruction is 128 bits:
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define <8 x i8> @vld2i8(ptr %A) nounwind {
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; CHECK-LABEL: vld2i8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.8 {d16, d17}, [r0:64]
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; CHECK-NEXT: vadd.i8 d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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;Check the alignment value. Max for this instruction is 128 bits:
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define <4 x i16> @vld2i16(ptr %A) nounwind {
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; CHECK-LABEL: vld2i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.16 {d16, d17}, [r0:128]
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; CHECK-NEXT: vadd.i16 d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
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%tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vld2i32(ptr %A) nounwind {
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; CHECK-LABEL: vld2i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
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; CHECK-NEXT: vadd.i32 d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
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%tmp4 = add <2 x i32> %tmp2, %tmp3
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ret <2 x i32> %tmp4
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}
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define <2 x float> @vld2f(ptr %A) nounwind {
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; CHECK-LABEL: vld2f:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
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; CHECK-NEXT: vadd.f32 d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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ret <2 x float> %tmp4
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}
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;Check for a post-increment updating load.
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define <2 x float> @vld2f_update(ptr %ptr) nounwind {
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; CHECK-LABEL: vld2f_update:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ldr r3, [r0]
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; CHECK-NEXT: vld2.32 {d16, d17}, [r3]!
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; CHECK-NEXT: vadd.f32 d16, d16, d17
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: vmov r2, r1, d16
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov pc, lr
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%A = load ptr, ptr %ptr
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%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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%tmp5 = getelementptr float, ptr %A, i32 4
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store ptr %tmp5, ptr %ptr
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ret <2 x float> %tmp4
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}
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;Check the alignment value. Max for this instruction is 128 bits:
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define <1 x i64> @vld2i64(ptr %A) nounwind {
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; CHECK-LABEL: vld2i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: vadd.i64 d16, d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
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%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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;Check the alignment value. Max for this instruction is 256 bits:
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define <16 x i8> @vld2Qi8(ptr %A) nounwind {
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; CHECK-LABEL: vld2Qi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [r0:64]
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; CHECK-NEXT: vadd.i8 q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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;Check for a post-increment updating load with register increment.
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define <16 x i8> @vld2Qi8_update(ptr %ptr, i32 %inc) nounwind {
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; CHECK-LABEL: vld2Qi8_update:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: ldr lr, [r0]
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; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [lr:128], r1
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; CHECK-NEXT: vadd.i8 q8, q8, q9
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; CHECK-NEXT: str lr, [r0]
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; CHECK-NEXT: vmov r12, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%A = load ptr, ptr %ptr
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%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
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%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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%tmp5 = getelementptr i8, ptr %A, i32 %inc
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store ptr %tmp5, ptr %ptr
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ret <16 x i8> %tmp4
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}
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;Check the alignment value. Max for this instruction is 256 bits:
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define <8 x i16> @vld2Qi16(ptr %A) nounwind {
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; CHECK-LABEL: vld2Qi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.16 {d16, d17, d18, d19}, [r0:128]
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; CHECK-NEXT: vadd.i16 q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
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%tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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;Check the alignment value. Max for this instruction is 256 bits:
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define <4 x i32> @vld2Qi32(ptr %A) nounwind {
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; CHECK-LABEL: vld2Qi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0:256]
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; CHECK-NEXT: vadd.i32 q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
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%tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld2Qf(ptr %A) nounwind {
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; CHECK-LABEL: vld2Qf:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0]
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; CHECK-NEXT: vadd.f32 q8, q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
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%tmp4 = fadd <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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define ptr @test_or_update(ptr %p, ptr %q) {
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; CHECK-LABEL: test_or_update:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r2, r0, #3
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; CHECK-NEXT: add r0, r0, #2
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; CHECK-NEXT: vld2.32 {d16, d17}, [r2]
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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%p1 = ptrtoint ptr %p to i32
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%p2 = or i32 %p1, 3
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%p3 = inttoptr i32 %p2 to ptr
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%l = load <4 x i32>, ptr %p3, align 1
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%s = shufflevector <4 x i32> %l, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
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store <2 x i32> %s, ptr %q
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%q1 = getelementptr i8, ptr %p, i32 2
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ret ptr %q1
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}
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