7064ff2226
This patch adds the HexagonGlobalScheduler, a post-packetization pass that performs global instruction scheduling and pull-up optimizations to improve packet density on Hexagon VLIW architecture. The scheduler operates on scheduling regions (super-blocks with single entry and multiple exits) and attempts to move instructions across basic blocks to fill packet slots more efficiently. It supports both speculative and predicative scheduling modes. Key features: - Global instruction scheduling across basic blocks - Speculative scheduling with safety checks - Predicative scheduling using predication - Local pull-up within basic blocks - Dual jump formation - Branch optimizations - Liveness preservation using HexagonLiveVariables The pass depends on HexagonLiveVariables and HexagonGlobalRegion infrastructure for maintaining correct liveness information when moving instructions across basic block boundaries. This patch also adds two helper functions to HexagonRegisterInfo that are required by the scheduler to prevent correctness issues. 1. isGlobalReg(MCPhysReg Reg) - Returns true for reserved physical registers (R29, R30, R31) that are live across function calls. This prevents the scheduler from incorrectly speculating instructions that modify the stack pointer or frame pointer. 2. isFakeReg(MCPhysReg Reg) - Returns true for fake HVX registers (VF0-VF31, VFR0-VFR31) used as sub-registers in vector pairs. This prevents crashes when the scheduler processes HVX vector operations by skipping these internal bookkeeping registers. The scheduler runs in the pre-emit pipeline after packetization and is only active when optimizations are enabled. This implementation includes fixes for iterator invalidation issues that could cause crashes when built with libstdc++ debug mode enabled. Original-work-by: Sergei Larin <slarin@qti.qualcomm.com> Co-authored-by: Ikhlas Ajbar <iajbar@qti.qualcomm.com> Co-authored-by: Krzysztof Parzyszek <kparzysz@codeaurora.org> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv73 -debug < %s
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; This test used to ICE with "[MIisDualJumpCandidate] To BB(0) From BB(1)".
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;REQUIRES: asserts
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target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon-unknown--elf"
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define void @main(i1 %cond) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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entry:
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br label %for.body.ur.i.i
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for.body.ur.i.i: ; preds = %for.body.ur.i.i, %entry
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br i1 %cond, label %for.inc26.6, label %for.body.ur.i.i
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invoke.cont: ; preds = %for.inc26.6
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%call.i.i.i.i174 = invoke noalias i8* @_Znwj()
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to label %_ZNSt6vectorIlSaIlEE12_Construct_nEjRKl.exit unwind label %lpad
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lpad: ; preds = %for.inc26.6, %invoke.cont
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%0 = landingpad { i8*, i32 }
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cleanup
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resume { i8*, i32 } %0
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_ZNSt6vectorIlSaIlEE12_Construct_nEjRKl.exit: ; preds = %invoke.cont
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%incdec.ptr.i.ur.i.1 = getelementptr inbounds i8, i8* %call.i.i.i.i174, i32 36
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call void @llvm.memset.p0i8.i64(i8* %call.i.i.i.i174, i8 0, i64 36, i32 4, i1 false)
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call void @llvm.memset.p0i8.i64(i8* %incdec.ptr.i.ur.i.1, i8 0, i64 32, i32 4, i1 false)
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unreachable
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for.inc26.6: ; preds = %for.body.ur.i.i
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invoke void @_ZNSt6vectorIlSaIlEE7_InsertIPlEEvSt16_Vector_iteratorIlS0_ET_S6_St20forward_iterator_tag()
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to label %invoke.cont unwind label %lpad
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}
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declare i32 @__gxx_personality_v0(...)
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declare noalias i8* @_Znwj()
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declare void @_ZNSt6vectorIlSaIlEE7_InsertIPlEEvSt16_Vector_iteratorIlS0_ET_S6_St20forward_iterator_tag() align 2
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
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