28318d5db8
This logic was previously embedded in NVPTXLowerArgs, but is split into a separate pass as it is an optional optimization orthogonal to kernel parameter lowering. This pass can be run earlier making alignment available to generic IR passes (like infer-alignment) and a separate pass makes the alignment logic independently testable. It also simplifies NVPTXLowerArgs by removing the duplicate handling of alignment for kernel vs. device functions.
37 lines
1.8 KiB
LLVM
37 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=nvptx-lower-args,infer-alignment -S | FileCheck %s
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target triple = "nvptx64-nvidia-cuda"
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; ------------------------------------------------------------------------------
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; Test that alignment can be inferred through llvm.nvvm.internal.addrspace.wrap.p101.p0 intrinsics
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; thanks to the alignment attribute on the intrinsic
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; ------------------------------------------------------------------------------
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%struct.S1 = type { i32, i32, i32, i32 }
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define ptx_kernel i32 @test_align8(ptr noundef readonly byval(%struct.S1) align 8 captures(none) %params) {
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; CHECK-LABEL: define ptx_kernel i32 @test_align8(
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; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 8 captures(none) "nvvm.grid_constant" [[PARAMS:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = call align 8 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])
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; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 8
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; CHECK-NEXT: ret i32 [[LOAD]]
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;
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entry:
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%load = load i32, ptr %params, align 4
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ret i32 %load
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}
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define ptx_kernel i32 @test_align1(ptr noundef readonly byval(%struct.S1) align 4 captures(none) %params) {
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; CHECK-LABEL: define ptx_kernel i32 @test_align1(
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; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 4 captures(none) "nvvm.grid_constant" [[PARAMS:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])
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; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 4
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; CHECK-NEXT: ret i32 [[LOAD]]
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;
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entry:
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%load = load i32, ptr %params, align 4
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ret i32 %load
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}
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