56a4315ee0
This is a relatively simple strategy as it is omitting any heuristics for liveness and register pressure reduction. This works well as the SystemZ ISel scheduler is using Sched::RegPressure which gives a good input order to begin with. It is trying harder with biasing phys regs than GenericScheduler as it also considers other instructions such as immediate loads directly into phys-regs produced by the register coalescer. This can hopefully be refactored into MachineScheduler.cpp. It has a latency heuristic that is slightly different from the one in GenericScheduler: It is activated for a specific type of region that have many "data sequences" consisting of SUs connected only with a single data-edge that are next to each other in the input order. This is only 3% of all the scheduling regions, but when activated it is applied on all the candidates (not just once per cycle). At the same time it is a bit more careful by checking not only the SU Height against the scheduled latency but also its Depth against the remaining latency. It reuses the GenericScheduler handling of weak edges to help copy coalescing. It also helps with compare zero elimination as it tries to put a CC-defining instruction that produces the compare source value above the compare before any other instruction clobbering CC or the value. This work was started after observing heavy spilling in Cactus, which was actually *caused* by GenericScheduler - disabling it (no pre-RA scheduling) remedied it and gave a 7% improvement in performance on that benchmark. Many different versions have been tried which has evolved into this initial simplistic MachineSchedStrategy that does relatively little and yet achieves double-digit improvements on Cactus and Imagick compared to GenericSched (which is OTOH 3% better on Blender). There will hopefully be more improvements added later on as there seems to be potential for it. It would be very interesting to have other OOO targets try this as well and perhaps make this available in MachineScheduler.cpp (A first attempt with improving the pre-RA scheduling was made with #90181, which however did not materialize in anything actually useful.)
143 lines
6.6 KiB
LLVM
143 lines
6.6 KiB
LLVM
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
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;
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; Check that the second load of @g_2 is not incorrectly eliminated by
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; DAGCombiner. It is needed since the preceding store is aliasing.
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; %.b1.i = load i1, ptr @g_2, align 4
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; ...
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; %g_717.sink.i = select i1 %cmp.i, ptr @g_717, ptr @g_2
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; store i1 true, ptr %g_717.sink.i, align 4
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; %.b = load i1, ptr @g_2, align 4
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; CHECK: # %bb.6: # %crc32_gentab.exit
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; CHECK: larl [[REG:%r[1-9]+]], g_2
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; CHECK-NEXT: llc {{%r[1-9]}}, 0([[REG]])
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; CHECK-NOT: [[REG]],
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; CHECK: llc %r1, 0([[REG]])
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@g_2 = external hidden unnamed_addr global i1, align 4
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@.str.1 = external hidden unnamed_addr constant [4 x i8], align 2
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@g_717 = external hidden unnamed_addr global i1, align 4
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@.str.2 = external hidden unnamed_addr constant [6 x i8], align 2
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@crc32_context = external hidden unnamed_addr global i32, align 4
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@crc32_tab = external hidden unnamed_addr global [256 x i32], align 4
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@g_5 = external hidden unnamed_addr global i32, align 4
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@.str.4 = external hidden unnamed_addr constant [15 x i8], align 2
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; Function Attrs: nounwind
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define signext i32 @main(i32 signext %argc, ptr nocapture readonly %argv) local_unnamed_addr #0 {
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entry:
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%cmp = icmp eq i32 %argc, 2
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br i1 %cmp, label %cond.true, label %vector.ph
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cond.true: ; preds = %entry
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%arrayidx = getelementptr inbounds ptr, ptr %argv, i64 1
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%0 = load ptr, ptr %arrayidx, align 8, !tbaa !2
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%1 = load i8, ptr %0, align 1, !tbaa !6
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%conv4 = zext i8 %1 to i32
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%sub = sub nsw i32 49, %conv4
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%cmp8 = icmp eq i32 %sub, 0
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br i1 %cmp8, label %if.then, label %if.end35
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if.then: ; preds = %cond.true
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%arrayidx11 = getelementptr inbounds i8, ptr %0, i64 1
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%2 = load i8, ptr %arrayidx11, align 1, !tbaa !6
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%conv12 = zext i8 %2 to i32
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%sub13 = sub nsw i32 0, %conv12
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br label %if.end35
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if.end35: ; preds = %if.then, %cond.true
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%__result.0 = phi i32 [ %sub13, %if.then ], [ %sub, %cond.true ]
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%phitmp = icmp eq i32 %__result.0, 0
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%spec.select = zext i1 %phitmp to i32
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br label %vector.ph
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vector.ph: ; preds = %if.end35, %entry
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%print_hash_value.0 = phi i32 [ 0, %entry ], [ %spec.select, %if.end35 ]
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.ind22 = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next23, %vector.body ]
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%3 = and <4 x i32> %vec.ind22, <i32 1, i32 1, i32 1, i32 1>
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%4 = icmp eq <4 x i32> %3, zeroinitializer
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%5 = lshr <4 x i32> %vec.ind22, <i32 1, i32 1, i32 1, i32 1>
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%6 = xor <4 x i32> %5, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%7 = select <4 x i1> %4, <4 x i32> %5, <4 x i32> %6
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%8 = and <4 x i32> %7, <i32 1, i32 1, i32 1, i32 1>
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%9 = icmp eq <4 x i32> %8, zeroinitializer
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%10 = lshr <4 x i32> %7, <i32 1, i32 1, i32 1, i32 1>
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%11 = xor <4 x i32> %10, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%12 = select <4 x i1> %9, <4 x i32> %10, <4 x i32> %11
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%13 = and <4 x i32> %12, <i32 1, i32 1, i32 1, i32 1>
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%14 = icmp eq <4 x i32> %13, zeroinitializer
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%15 = lshr <4 x i32> %12, <i32 1, i32 1, i32 1, i32 1>
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%16 = xor <4 x i32> %15, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%17 = select <4 x i1> %14, <4 x i32> %15, <4 x i32> %16
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%18 = and <4 x i32> %17, <i32 1, i32 1, i32 1, i32 1>
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%19 = icmp eq <4 x i32> %18, zeroinitializer
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%20 = lshr <4 x i32> %17, <i32 1, i32 1, i32 1, i32 1>
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%21 = xor <4 x i32> %20, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%22 = select <4 x i1> %19, <4 x i32> %20, <4 x i32> %21
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%23 = and <4 x i32> %22, <i32 1, i32 1, i32 1, i32 1>
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%24 = icmp eq <4 x i32> %23, zeroinitializer
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%25 = lshr <4 x i32> %22, <i32 1, i32 1, i32 1, i32 1>
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%26 = xor <4 x i32> %25, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%27 = select <4 x i1> %24, <4 x i32> %25, <4 x i32> %26
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%28 = and <4 x i32> %27, <i32 1, i32 1, i32 1, i32 1>
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%29 = icmp eq <4 x i32> %28, zeroinitializer
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%30 = lshr <4 x i32> %27, <i32 1, i32 1, i32 1, i32 1>
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%31 = xor <4 x i32> %30, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%32 = select <4 x i1> %29, <4 x i32> %30, <4 x i32> %31
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%33 = and <4 x i32> %32, <i32 1, i32 1, i32 1, i32 1>
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%34 = icmp eq <4 x i32> %33, zeroinitializer
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%35 = lshr <4 x i32> %32, <i32 1, i32 1, i32 1, i32 1>
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%36 = xor <4 x i32> %35, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%37 = select <4 x i1> %34, <4 x i32> %35, <4 x i32> %36
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%38 = and <4 x i32> %37, <i32 1, i32 1, i32 1, i32 1>
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%39 = icmp eq <4 x i32> %38, zeroinitializer
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%40 = lshr <4 x i32> %37, <i32 1, i32 1, i32 1, i32 1>
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%41 = xor <4 x i32> %40, <i32 -306674912, i32 -306674912, i32 -306674912, i32 -306674912>
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%42 = select <4 x i1> %39, <4 x i32> %40, <4 x i32> %41
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%43 = getelementptr inbounds [256 x i32], ptr @crc32_tab, i64 0, i64 %index
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store <4 x i32> %42, ptr %43, align 4, !tbaa !7
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%index.next = add i64 %index, 4
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%vec.ind.next23 = add <4 x i32> %vec.ind22, <i32 4, i32 4, i32 4, i32 4>
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%44 = icmp eq i64 %index.next, 256
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br i1 %44, label %crc32_gentab.exit, label %vector.body
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crc32_gentab.exit: ; preds = %vector.body
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%45 = load i32, ptr @g_5, align 4, !tbaa !7
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%.b1.i = load i1, ptr @g_2, align 4
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%46 = select i1 %.b1.i, i32 1, i32 2
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%and.i21 = and i32 %46, %45
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store i32 %and.i21, ptr @g_5, align 4, !tbaa !7
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%cmp.i = icmp eq i32 %and.i21, 1
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%g_717.sink.i = select i1 %cmp.i, ptr @g_717, ptr @g_2
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store i1 true, ptr %g_717.sink.i, align 4
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%.b = load i1, ptr @g_2, align 4
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%conv44 = select i1 %.b, i64 1, i64 2
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tail call fastcc void @transparent_crc(i64 %conv44, ptr @.str.1, i32 signext %print_hash_value.0)
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%.b20 = load i1, ptr @g_717, align 4
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%conv45 = select i1 %.b20, i64 2, i64 0
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tail call fastcc void @transparent_crc(i64 %conv45, ptr @.str.2, i32 signext %print_hash_value.0)
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%47 = load i32, ptr @crc32_context, align 4, !tbaa !7
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%48 = xor i32 %47, -1
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%call.i = tail call signext i32 (ptr, ...) @printf(ptr @.str.4, i32 zeroext %48) #2
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ret i32 0
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}
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; Function Attrs: nounwind
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declare hidden fastcc void @transparent_crc(i64, ptr, i32 signext) unnamed_addr #0
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; Function Attrs: nounwind
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declare signext i32 @printf(ptr nocapture readonly, ...) local_unnamed_addr #1
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!2 = !{!3, !3, i64 0}
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!3 = !{!"any pointer", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!4, !4, i64 0}
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!7 = !{!8, !8, i64 0}
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!8 = !{!"int", !4, i64 0}
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