56a4315ee0
This is a relatively simple strategy as it is omitting any heuristics for liveness and register pressure reduction. This works well as the SystemZ ISel scheduler is using Sched::RegPressure which gives a good input order to begin with. It is trying harder with biasing phys regs than GenericScheduler as it also considers other instructions such as immediate loads directly into phys-regs produced by the register coalescer. This can hopefully be refactored into MachineScheduler.cpp. It has a latency heuristic that is slightly different from the one in GenericScheduler: It is activated for a specific type of region that have many "data sequences" consisting of SUs connected only with a single data-edge that are next to each other in the input order. This is only 3% of all the scheduling regions, but when activated it is applied on all the candidates (not just once per cycle). At the same time it is a bit more careful by checking not only the SU Height against the scheduled latency but also its Depth against the remaining latency. It reuses the GenericScheduler handling of weak edges to help copy coalescing. It also helps with compare zero elimination as it tries to put a CC-defining instruction that produces the compare source value above the compare before any other instruction clobbering CC or the value. This work was started after observing heavy spilling in Cactus, which was actually *caused* by GenericScheduler - disabling it (no pre-RA scheduling) remedied it and gave a 7% improvement in performance on that benchmark. Many different versions have been tried which has evolved into this initial simplistic MachineSchedStrategy that does relatively little and yet achieves double-digit improvements on Cactus and Imagick compared to GenericSched (which is OTOH 3% better on Blender). There will hopefully be more improvements added later on as there seems to be potential for it. It would be very interesting to have other OOO targets try this as well and perhaps make this available in MachineScheduler.cpp (A first attempt with improving the pre-RA scheduling was made with #90181, which however did not materialize in anything actually useful.)
245 lines
7.4 KiB
LLVM
245 lines
7.4 KiB
LLVM
; Test memcpy using MVC.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc -mtriple=s390x-linux-gnu -filetype=null %s
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declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
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declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind
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declare void @foo(ptr, ptr)
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; Test a no-op move, i32 version.
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define void @f1(ptr %dest, ptr %src) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r2
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; CHECK-NOT: %r3
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 0, i1 false)
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ret void
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}
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; Test a no-op move, i64 version.
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define void @f2(ptr %dest, ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r2
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; CHECK-NOT: %r3
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 0, i1 false)
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ret void
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}
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; Test a 1-byte move, i32 version.
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define void @f3(ptr %dest, ptr %src) {
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; CHECK-LABEL: f3:
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; CHECK: mvc 0(1,%r2), 0(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 1, i1 false)
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ret void
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}
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; Test a 1-byte move, i64 version.
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define void @f4(ptr %dest, ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: mvc 0(1,%r2), 0(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1, i1 false)
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ret void
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}
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; Test the upper range of a single MVC, i32 version.
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define void @f5(ptr %dest, ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 256, i1 false)
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ret void
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}
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; Test the upper range of a single MVC, i64 version.
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define void @f6(ptr %dest, ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 256, i1 false)
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ret void
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}
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; Test the first case that needs two MVCs.
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define void @f7(ptr %dest, ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: mvc 256(1,%r2), 256(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i32(ptr %dest, ptr %src, i32 257, i1 false)
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ret void
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}
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; Test the last-but-one case that needs two MVCs.
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define void @f8(ptr %dest, ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: mvc 256(255,%r2), 256(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 511, i1 false)
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ret void
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}
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; Test the last case that needs two MVCs.
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define void @f9(ptr %dest, ptr %src) {
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; CHECK-LABEL: f9:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: mvc 256(256,%r2), 256(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 512, i1 false)
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ret void
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}
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; Test an arbitrary value that uses straight-line code.
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define void @f10(ptr %dest, ptr %src) {
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; CHECK-LABEL: f10:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: mvc 256(256,%r2), 256(%r3)
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; CHECK: mvc 512(256,%r2), 512(%r3)
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; CHECK: mvc 768(256,%r2), 768(%r3)
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; CHECK: mvc 1024(255,%r2), 1024(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1279, i1 false)
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ret void
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}
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; ...and again in cases where not all parts are in range of MVC.
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define void @f11(ptr %srcbase, ptr %destbase) {
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; CHECK-LABEL: f11:
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; CHECK: mvc 4000(256,%r2), 3500(%r3)
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; CHECK: lay [[NEWDEST:%r[1-5]]], 4256(%r2)
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; CHECK: mvc 0(256,[[NEWDEST]]), 3756(%r3)
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; CHECK: mvc 256(256,[[NEWDEST]]), 4012(%r3)
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; CHECK: lay [[NEWSRC:%r[1-5]]], 4268(%r3)
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; CHECK: mvc 512(256,[[NEWDEST]]), 0([[NEWSRC]])
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; CHECK: mvc 768(255,[[NEWDEST]]), 256([[NEWSRC]])
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; CHECK: br %r14
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%dest = getelementptr i8, ptr %srcbase, i64 4000
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%src = getelementptr i8, ptr %destbase, i64 3500
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1279, i1 false)
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ret void
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}
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; ...and again with a destination frame base that goes out of range.
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define void @f12() {
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; CHECK-LABEL: f12:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: mvc 4076(256,%r15), 2100(%r15)
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; CHECK: lay [[NEWDEST:%r[1-5]]], 4332(%r15)
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; CHECK: mvc 0(256,[[NEWDEST]]), 2356(%r15)
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; CHECK: mvc 256(256,[[NEWDEST]]), 2612(%r15)
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; CHECK: mvc 512(256,[[NEWDEST]]), 2868(%r15)
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; CHECK: mvc 768(255,[[NEWDEST]]), 3124(%r15)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%arr = alloca [6000 x i8]
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%dest = getelementptr [6000 x i8], ptr %arr, i64 0, i64 3900
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%src = getelementptr [6000 x i8], ptr %arr, i64 0, i64 1924
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call void @foo(ptr %dest, ptr %src)
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1279, i1 false)
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call void @foo(ptr %dest, ptr %src)
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ret void
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}
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; ...and again with a source frame base that goes out of range.
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define void @f13() {
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; CHECK-LABEL: f13:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: mvc 200(256,%r15), 3826(%r15)
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; CHECK-DAG: mvc 456(256,%r15), 4082(%r15)
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; CHECK-DAG: lay [[NEWSRC:%r[1-5]]], 4338(%r15)
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; CHECK: mvc 712(256,%r15), 0([[NEWSRC]])
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; CHECK: mvc 968(256,%r15), 256([[NEWSRC]])
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; CHECK: mvc 1224(255,%r15), 512([[NEWSRC]])
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%arr = alloca [6000 x i8]
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%dest = getelementptr [6000 x i8], ptr %arr, i64 0, i64 24
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%src = getelementptr [6000 x i8], ptr %arr, i64 0, i64 3650
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call void @foo(ptr %dest, ptr %src)
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1279, i1 false)
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call void @foo(ptr %dest, ptr %src)
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ret void
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}
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; Test the last case that is done using straight-line code.
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define void @f14(ptr %dest, ptr %src) {
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; CHECK-LABEL: f14:
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: mvc 256(256,%r2), 256(%r3)
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; CHECK: mvc 512(256,%r2), 512(%r3)
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; CHECK: mvc 768(256,%r2), 768(%r3)
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; CHECK: mvc 1024(256,%r2), 1024(%r3)
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; CHECK: mvc 1280(256,%r2), 1280(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1536, i1 false)
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ret void
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}
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; Test the first case that is done using a loop.
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define void @f15(ptr %dest, ptr %src) {
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; CHECK-LABEL: f15:
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; CHECK: lghi [[COUNT:%r[0-5]]], 6
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; CHECK: [[LABEL:\.L[^:]*]]:
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; CHECK: pfd 2, 768(%r2)
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; CHECK: mvc 0(256,%r2), 0(%r3)
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; CHECK: la %r2, 256(%r2)
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; CHECK: la %r3, 256(%r3)
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; CHECK: brctg [[COUNT]], [[LABEL]]
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; CHECK: mvc 0(1,%r2), 0(%r3)
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; CHECK: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 1537, i1 false)
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ret void
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}
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; ...and again with frame bases, where the base must be loaded into a
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; register before the loop.
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define void @f16() {
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; CHECK-LABEL: f16:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-DAG: lghi [[COUNT:%r[0-5]]], 6
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; CHECK-DAG: la [[BASE:%r[0-5]]], 160(%r15)
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; CHECK: [[LABEL:\.L[^:]*]]:
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; CHECK: pfd 2, 2368([[BASE]])
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; CHECK: mvc 1600(256,[[BASE]]), 0([[BASE]])
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; CHECK: la [[BASE]], 256([[BASE]])
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; CHECK: brctg [[COUNT]], [[LABEL]]
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; CHECK: mvc 1600(1,[[BASE]]), 0([[BASE]])
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%arr = alloca [3200 x i8]
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%dest = getelementptr [3200 x i8], ptr %arr, i64 0, i64 1600
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call void @foo(ptr %dest, ptr %arr)
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %arr, i64 1537, i1 false)
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call void @foo(ptr %dest, ptr %arr)
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ret void
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}
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; Test a variable length loop.
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define void @f17(ptr %dest, ptr %src, i64 %Len) {
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; CHECK-LABEL: f17:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aghi %r4, -1
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; CHECK-NEXT: cgibe %r4, -1, 0(%r14)
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; CHECK-NEXT: .LBB16_1:
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; CHECK-NEXT: srlg %r0, %r4, 8
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; CHECK-NEXT: cgije %r0, 0, .LBB16_3
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; CHECK-NEXT: .LBB16_2: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: pfd 2, 768(%r2)
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; CHECK-NEXT: mvc 0(256,%r2), 0(%r3)
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; CHECK-NEXT: la %r2, 256(%r2)
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; CHECK-NEXT: la %r3, 256(%r3)
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; CHECK-NEXT: brctg %r0, .LBB16_2
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; CHECK-NEXT: .LBB16_3:
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; CHECK-NEXT: exrl %r4, .Ltmp0
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; CHECK-NEXT: br %r14
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call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 %Len, i1 false)
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ret void
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}
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; CHECK: .Ltmp0:
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; CHECK-NEXT: mvc 0(1,%r2), 0(%r3)
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