56a4315ee0
This is a relatively simple strategy as it is omitting any heuristics for liveness and register pressure reduction. This works well as the SystemZ ISel scheduler is using Sched::RegPressure which gives a good input order to begin with. It is trying harder with biasing phys regs than GenericScheduler as it also considers other instructions such as immediate loads directly into phys-regs produced by the register coalescer. This can hopefully be refactored into MachineScheduler.cpp. It has a latency heuristic that is slightly different from the one in GenericScheduler: It is activated for a specific type of region that have many "data sequences" consisting of SUs connected only with a single data-edge that are next to each other in the input order. This is only 3% of all the scheduling regions, but when activated it is applied on all the candidates (not just once per cycle). At the same time it is a bit more careful by checking not only the SU Height against the scheduled latency but also its Depth against the remaining latency. It reuses the GenericScheduler handling of weak edges to help copy coalescing. It also helps with compare zero elimination as it tries to put a CC-defining instruction that produces the compare source value above the compare before any other instruction clobbering CC or the value. This work was started after observing heavy spilling in Cactus, which was actually *caused* by GenericScheduler - disabling it (no pre-RA scheduling) remedied it and gave a 7% improvement in performance on that benchmark. Many different versions have been tried which has evolved into this initial simplistic MachineSchedStrategy that does relatively little and yet achieves double-digit improvements on Cactus and Imagick compared to GenericSched (which is OTOH 3% better on Blender). There will hopefully be more improvements added later on as there seems to be potential for it. It would be very interesting to have other OOO targets try this as well and perhaps make this available in MachineScheduler.cpp (A first attempt with improving the pre-RA scheduling was made with #90181, which however did not materialize in anything actually useful.)
221 lines
5.9 KiB
LLVM
221 lines
5.9 KiB
LLVM
; Test memset in cases where the set value is variable.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
|
|
declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
|
|
|
|
; No bytes, i32 version.
|
|
define void @f1(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK-NOT: %r2
|
|
; CHECK-NOT: %r3
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; No bytes, i64 version.
|
|
define void @f2(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK-NOT: %r2
|
|
; CHECK-NOT: %r3
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 1 byte, i32 version.
|
|
define void @f3(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 1, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 1 byte, i64 version.
|
|
define void @f4(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 1, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 2 bytes, i32 version.
|
|
define void @f5(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f5:
|
|
; CHECK-DAG: stc %r3, 0(%r2)
|
|
; CHECK-DAG: stc %r3, 1(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 2, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 2 bytes, i64 version.
|
|
define void @f6(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f6:
|
|
; CHECK-DAG: stc %r3, 0(%r2)
|
|
; CHECK-DAG: stc %r3, 1(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 2, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 3 bytes, i32 version.
|
|
define void @f7(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f7:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(2,%r2), 0(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 3, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 3 bytes, i64 version.
|
|
define void @f8(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f8:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(2,%r2), 0(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 3, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 257 bytes, i32 version.
|
|
define void @f9(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f9:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: stc %r3, 256(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 257, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 257 bytes, i64 version.
|
|
define void @f10(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f10:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: stc %r3, 256(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 257, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 258 bytes, i32 version. We need two MVCs.
|
|
define void @f11(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f11:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: stc %r3, 256(%r2)
|
|
; CHECK: mvc 257(1,%r2), 256(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i32(ptr %dest, i8 %val, i32 258, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; 258 bytes, i64 version.
|
|
define void @f12(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f12:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: stc %r3, 256(%r2)
|
|
; CHECK: mvc 257(1,%r2), 256(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 258, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test the largest case for which straight-line code is used.
|
|
define void @f13(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f13:
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: stc %r3, 256(%r2)
|
|
; CHECK: mvc 257(255,%r2), 256(%r2)
|
|
; CHECK: stc %r3, 512(%r2)
|
|
; CHECK: mvc 513(255,%r2), 512(%r2)
|
|
; CHECK: stc %r3, 768(%r2)
|
|
; CHECK: mvc 769(255,%r2), 768(%r2)
|
|
; CHECK: stc %r3, 1024(%r2)
|
|
; CHECK: mvc 1025(255,%r2), 1024(%r2)
|
|
; CHECK: stc %r3, 1280(%r2)
|
|
; CHECK: mvc 1281(255,%r2), 1280(%r2)
|
|
; CHECK: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 1536, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test the next size up, which uses a loop. We leave the other corner
|
|
; cases to memcpy-01.ll and memset-07.ll.
|
|
define void @f14(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f14:
|
|
; CHECK: lghi [[COUNT:%r[0-5]]], 6
|
|
; CHECK: [[LABEL:\.L[^:]*]]:
|
|
; CHECK: pfd 2, 768(%r2)
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK: mvc 1(255,%r2), 0(%r2)
|
|
; CHECK: la %r2, 256(%r2)
|
|
; CHECK: brctg [[COUNT]], [[LABEL]]
|
|
; CHECK: stc %r3, 0(%r2)
|
|
; CHECK-NEXT: br %r14
|
|
call void @llvm.memset.p0.i64(ptr %dest, i8 %val, i64 1537, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test (no) folding of displacement: Begins with max(uint12) - 1.
|
|
define void @f15(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f15:
|
|
; CHECK-NOT: la {{.*}}%r2
|
|
%addr = getelementptr i8, ptr %dest, i64 4094
|
|
call void @llvm.memset.p0.i64(ptr %addr, i8 %val, i64 256, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test folding of displacement: Begins with max(uint12).
|
|
define void @f16(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f16:
|
|
; CHECK-DAG: lay %r1, 4096(%r2)
|
|
; CHECK-DAG: stc %r3, 4095(%r2)
|
|
%addr = getelementptr i8, ptr %dest, i64 4095
|
|
call void @llvm.memset.p0.i64(ptr %addr, i8 %val, i64 256, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test folding of displacement with LA: First two ops are in range.
|
|
define void @f17(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f17:
|
|
; CHECK: stc %r3, 3583(%r2)
|
|
; CHECK-NEXT: mvc 3584(255,%r2), 3583(%r2)
|
|
; CHECK-NEXT: stc %r3, 3839(%r2)
|
|
; CHECK-NEXT: mvc 3840(255,%r2), 3839(%r2)
|
|
; CHECK-DAG: lay %r1, 4096(%r2)
|
|
; CHECK-DAG: stc %r3, 4095(%r2)
|
|
; CHECK-NEXT: mvc 0(1,%r1), 4095(%r2)
|
|
; CHECK-NEXT: br %r14
|
|
%addr = getelementptr i8, ptr %dest, i64 3583
|
|
call void @llvm.memset.p0.i64(ptr %addr, i8 %val, i64 514, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Test folding of displacement with LAY: First two ops are in range.
|
|
define void @f18(ptr %dest, i8 %val) {
|
|
; CHECK-LABEL: f18:
|
|
; CHECK: stc %r3, 3584(%r2)
|
|
; CHECK-NEXT: mvc 3585(255,%r2), 3584(%r2)
|
|
; CHECK-NEXT: stc %r3, 3840(%r2)
|
|
; CHECK-NEXT: mvc 3841(255,%r2), 3840(%r2)
|
|
; CHECK-NEXT: lay %r1, 4097(%r2)
|
|
; CHECK-NEXT: lay %r2, 4096(%r2)
|
|
; CHECK-NEXT: stc %r3, 0(%r2)
|
|
; CHECK-NEXT: mvc 0(1,%r1), 0(%r2)
|
|
; CHECK-NEXT: br %r14
|
|
%addr = getelementptr i8, ptr %dest, i64 3584
|
|
call void @llvm.memset.p0.i64(ptr %addr, i8 %val, i64 514, i1 false)
|
|
ret void
|
|
}
|
|
|