c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
148 lines
4.4 KiB
LLVM
148 lines
4.4 KiB
LLVM
; Test stores of element-swapped vector elements.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
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; Test v16i8 stores.
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define void @f1(<16 x i8> %val, ptr %ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vstbrq %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <16 x i8> %val, <16 x i8> undef,
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<16 x i32> <i32 15, i32 14, i32 13, i32 12,
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i32 11, i32 10, i32 9, i32 8,
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i32 7, i32 6, i32 5, i32 4,
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i32 3, i32 2, i32 1, i32 0>
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store <16 x i8> %swap, ptr %ptr
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ret void
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}
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; Test v8i16 stores.
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define void @f2(<8 x i16> %val, ptr %ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vsterh %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <8 x i16> %val, <8 x i16> undef,
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<8 x i32> <i32 7, i32 6, i32 5, i32 4,
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i32 3, i32 2, i32 1, i32 0>
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store <8 x i16> %swap, ptr %ptr
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ret void
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}
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; Test v4i32 stores.
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define void @f3(<4 x i32> %val, ptr %ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vsterf %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %ptr
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ret void
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}
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; Test v2i64 stores.
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define void @f4(<2 x i64> %val, ptr %ptr) {
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; CHECK-LABEL: f4:
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; CHECK: vsterg %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <2 x i64> %val, <2 x i64> undef,
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<2 x i32> <i32 1, i32 0>
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store <2 x i64> %swap, ptr %ptr
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ret void
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}
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; Test v8f16 stores.
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define void @f5(<8 x half> %val, ptr %ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vsterh %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <8 x half> %val, <8 x half> undef,
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<8 x i32> <i32 7, i32 6, i32 5, i32 4,
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i32 3, i32 2, i32 1, i32 0>
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store <8 x half> %swap, ptr %ptr
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ret void
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}
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; Test v4f32 stores.
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define void @f6(<4 x float> %val, ptr %ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vsterf %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <4 x float> %val, <4 x float> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x float> %swap, ptr %ptr
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ret void
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}
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; Test v2f64 stores.
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define void @f7(<2 x double> %val, ptr %ptr) {
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; CHECK-LABEL: f7:
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; CHECK: vsterg %v24, 0(%r2)
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; CHECK: br %r14
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%swap = shufflevector <2 x double> %val, <2 x double> undef,
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<2 x i32> <i32 1, i32 0>
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store <2 x double> %swap, ptr %ptr
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ret void
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}
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; Test the highest aligned in-range offset.
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define void @f8(<4 x i32> %val, ptr %base) {
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; CHECK-LABEL: f8:
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; CHECK: vsterf %v24, 4080(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, ptr %base, i64 255
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %ptr
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ret void
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}
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; Test the highest unaligned in-range offset.
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define void @f9(<4 x i32> %val, ptr %base) {
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; CHECK-LABEL: f9:
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; CHECK: vsterf %v24, 4095(%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, ptr %base, i64 4095
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %addr, align 1
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ret void
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}
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; Test the next offset up, which requires separate address logic,
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define void @f10(<4 x i32> %val, ptr %base) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, 4096
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; CHECK: vsterf %v24, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, ptr %base, i64 256
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %ptr
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ret void
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}
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; Test negative offsets, which also require separate address logic,
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define void @f11(<4 x i32> %val, ptr %base) {
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; CHECK-LABEL: f11:
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; CHECK: aghi %r2, -16
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; CHECK: vsterf %v24, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, ptr %base, i64 -1
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %ptr
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ret void
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}
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; Check that indexes are allowed.
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define void @f12(<4 x i32> %val, ptr %base, i64 %index) {
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; CHECK-LABEL: f12:
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; CHECK: vsterf %v24, 0(%r3,%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, ptr %base, i64 %index
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%swap = shufflevector <4 x i32> %val, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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store <4 x i32> %swap, ptr %addr, align 1
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ret void
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}
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