c752bb9203
When reviewing another change, I noticed that we were failing to infer samsign for two cases: 1) an unsigned comparison, and 2) when both arguments were known negative. Using CVP and InstCombine as a reference, we need to be careful to not allow eq/ne comparisons. I'm a bit unclear on the why of that, and for now am going with the low risk change. I may return to investigate that in a follow up. Compile time results look like noise to me, see: https://llvm-compile-time-tracker.com/compare.php?from=49a978712893fcf9e5f40ac488315d029cf15d3d&to=2ddb263604fd7d538e09dc1f805ebc30eb3ffab0&stat=instructions:u
145 lines
6.0 KiB
LLVM
145 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=indvars < %s | FileCheck %s
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; We must NOT replace check against IV with check against invariant 0. It should fail.
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define i32 @test_01() {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[OUTER_LOOP:%.*]]
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; CHECK: outer.loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: [[CHECK_1:%.*]] = icmp ult i32 [[IV]], 2
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: inner.loop:
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; CHECK-NEXT: [[STOREMERGE611_I:%.*]] = phi i64 [ 0, [[OUTER_LOOP]] ], [ [[ADD_I:%.*]], [[INNER_LATCH:%.*]] ]
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; CHECK-NEXT: br i1 [[CHECK_1]], label [[INNER_LATCH]], label [[EXIT:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[ADD_I]] = add nuw nsw i64 [[STOREMERGE611_I]], 1
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; CHECK-NEXT: [[CMP5_I:%.*]] = icmp samesign ult i64 [[STOREMERGE611_I]], 11
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; CHECK-NEXT: br i1 [[CMP5_I]], label [[INNER_LOOP]], label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], -1
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; CHECK-NEXT: br label [[OUTER_LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[INNER_LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %outer.loop
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outer.loop: ; preds = %outer.latch, %entry
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %outer.latch ]
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%check_1 = icmp ult i32 %iv, 2
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br label %inner.loop
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inner.loop: ; preds = %inner.latch, %outer.loop
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%storemerge611.i = phi i64 [ 0, %outer.loop ], [ %add.i, %inner.latch ]
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br i1 %check_1, label %inner.latch, label %exit
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inner.latch: ; preds = %inner.loop
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%add.i = add i64 %storemerge611.i, 1
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%cmp5.i = icmp ult i64 %storemerge611.i, 11
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br i1 %cmp5.i, label %inner.loop, label %outer.latch
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outer.latch: ; preds = %inner.latch
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%iv.next = add i32 %iv, -1
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br label %outer.loop
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exit: ; preds = %inner.loop
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ret i32 %iv
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}
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define i32 @test_02() {
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; CHECK-LABEL: @test_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[OUTER_LOOP:%.*]]
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; CHECK: outer.loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: [[CHECK_1:%.*]] = icmp samesign ult i32 [[IV]], 2147483640
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: inner.loop:
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; CHECK-NEXT: [[STOREMERGE611_I:%.*]] = phi i64 [ 0, [[OUTER_LOOP]] ], [ [[ADD_I:%.*]], [[INNER_LATCH:%.*]] ]
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; CHECK-NEXT: br i1 [[CHECK_1]], label [[INNER_LATCH]], label [[EXIT:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[ADD_I]] = add nuw nsw i64 [[STOREMERGE611_I]], 1
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; CHECK-NEXT: [[CMP5_I:%.*]] = icmp samesign ult i64 [[STOREMERGE611_I]], 11
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; CHECK-NEXT: br i1 [[CMP5_I]], label [[INNER_LOOP]], label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 10
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; CHECK-NEXT: br label [[OUTER_LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[INNER_LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %outer.loop
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outer.loop: ; preds = %outer.latch, %entry
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %outer.latch ]
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%check_1 = icmp ult i32 %iv, 2147483640
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br label %inner.loop
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inner.loop: ; preds = %inner.latch, %outer.loop
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%storemerge611.i = phi i64 [ 0, %outer.loop ], [ %add.i, %inner.latch ]
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br i1 %check_1, label %inner.latch, label %exit
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inner.latch: ; preds = %inner.loop
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%add.i = add i64 %storemerge611.i, 1
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%cmp5.i = icmp ult i64 %storemerge611.i, 11
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br i1 %cmp5.i, label %inner.loop, label %outer.latch
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outer.latch: ; preds = %inner.latch
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%iv.next = add i32 %iv, 10
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br label %outer.loop
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exit: ; preds = %inner.loop
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ret i32 %iv
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}
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define i32 @test_03() {
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; CHECK-LABEL: @test_03(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[OUTER_LOOP:%.*]]
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; CHECK: outer.loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 2147483640, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: [[CHECK_1:%.*]] = icmp ult i32 [[IV]], 2147483647
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: inner.loop:
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; CHECK-NEXT: [[STOREMERGE611_I:%.*]] = phi i64 [ 0, [[OUTER_LOOP]] ], [ [[ADD_I:%.*]], [[INNER_LATCH:%.*]] ]
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; CHECK-NEXT: br i1 [[CHECK_1]], label [[INNER_LATCH]], label [[EXIT:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[ADD_I]] = add nuw nsw i64 [[STOREMERGE611_I]], 1
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; CHECK-NEXT: [[CMP5_I:%.*]] = icmp samesign ult i64 [[STOREMERGE611_I]], 11
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; CHECK-NEXT: br i1 [[CMP5_I]], label [[INNER_LOOP]], label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 10
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; CHECK-NEXT: br label [[OUTER_LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[INNER_LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %outer.loop
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outer.loop: ; preds = %outer.latch, %entry
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%iv = phi i32 [ 2147483640, %entry ], [ %iv.next, %outer.latch ]
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%check_1 = icmp ult i32 %iv, 2147483647
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br label %inner.loop
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inner.loop: ; preds = %inner.latch, %outer.loop
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%storemerge611.i = phi i64 [ 0, %outer.loop ], [ %add.i, %inner.latch ]
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br i1 %check_1, label %inner.latch, label %exit
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inner.latch: ; preds = %inner.loop
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%add.i = add i64 %storemerge611.i, 1
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%cmp5.i = icmp ult i64 %storemerge611.i, 11
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br i1 %cmp5.i, label %inner.loop, label %outer.latch
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outer.latch: ; preds = %inner.latch
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%iv.next = add i32 %iv, 10
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br label %outer.loop
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exit: ; preds = %inner.loop
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ret i32 %iv
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}
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