e8556ff6b6
This test is failing on the llvm-clang-x-aarch64 buildbot due to what looks like a difference in rounding behaviour when printing estimated cost per lane. Solve this by removing the fractional part, which is what we've done in the past when this has happened (e.g. commit aeb88f677).
118 lines
5.2 KiB
LLVM
118 lines
5.2 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth=false -debug-only=loop-vectorize,vplan -disable-output -force-vector-interleave=1 -enable-epilogue-vectorization=false -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOMAX
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; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth=true -debug-only=loop-vectorize,vplan -disable-output -force-vector-interleave=1 -enable-epilogue-vectorization=false -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-REGS-VP
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; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth=true -debug-only=loop-vectorize,vplan -disable-output -force-target-num-vector-regs=1 -force-vector-interleave=1 -enable-epilogue-vectorization=false -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOREGS-VP
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-none-unknown-elf"
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; The use of the dotp instruction means we never have an i32 vector, so we don't
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; get any spills normally and with a reduced number of registers the number of
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; spills is small enough that it doesn't prevent use of a larger VF.
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define i32 @dotp(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: LV: Checking a loop in 'dotp'
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;
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; CHECK-NOMAX: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-NOMAX: LV: Selecting VF: vscale x 4.
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;
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; CHECK-REGS-VP: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-REGS-VP: Cost for VF vscale x 8: 6 (Estimated cost per lane: 0.
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; CHECK-REGS-VP: Cost for VF vscale x 16: 5 (Estimated cost per lane: 0.
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; CHECK-REGS-VP: LV: Selecting VF: vscale x 16.
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;
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; CHECK-NOREGS-VP: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-NOREGS-VP: LV(REG): Cost of 4 from 2 spills of Generic::VectorRC
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; CHECK-NOREGS-VP-NEXT: Cost for VF vscale x 8: 14 (Estimated cost per lane: 1.
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; CHECK-NOREGS-VP: LV(REG): Cost of 4 from 2 spills of Generic::VectorRC
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; CHECK-NOREGS-VP-NEXT: Cost for VF vscale x 16: 13 (Estimated cost per lane: 0.
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; CHECK-NOREGS-VP: LV: Selecting VF: vscale x 16.
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%accum = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%gep.a = getelementptr i8, ptr %a, i64 %iv
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%load.a = load i8, ptr %gep.a, align 1
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%ext.a = zext i8 %load.a to i32
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%gep.b = getelementptr i8, ptr %b, i64 %iv
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%load.b = load i8, ptr %gep.b, align 1
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%ext.b = zext i8 %load.b to i32
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%mul = mul i32 %ext.b, %ext.a
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%add = add i32 %accum, %mul
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%iv.next = add i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, 1024
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br i1 %exitcond.not, label %for.exit, label %for.body
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for.exit: ; preds = %for.body
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ret i32 %add
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}
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; The largest type used in the loop is small enough that we already consider all
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; VFs and maximize-bandwidth does nothing.
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define void @type_too_small(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: LV: Checking a loop in 'type_too_small'
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; CHECK: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK: Cost for VF vscale x 8: 6 (Estimated cost per lane: 0.
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; CHECK: Cost for VF vscale x 16: 6 (Estimated cost per lane: 0.
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; CHECK: LV: Selecting VF: vscale x 16.
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.a = getelementptr i8, ptr %a, i64 %iv
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%load.a = load i8, ptr %gep.a, align 1
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%gep.b = getelementptr i8, ptr %b, i64 %iv
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%load.b = load i8, ptr %gep.b, align 1
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%add = add i8 %load.a, %load.b
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store i8 %add, ptr %gep.a, align 1
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%iv.next = add i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 1024
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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; With reduced number of registers the spills from high pressure are enough that
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; we use the same VF as if we hadn't maximized the bandwidth.
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define void @high_pressure(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: LV: Checking a loop in 'high_pressure'
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;
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; CHECK-NOMAX: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-NOMAX: LV: Selecting VF: vscale x 4.
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;
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; CHECK-REGS-VP: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-REGS-VP: Cost for VF vscale x 8: 10 (Estimated cost per lane: 1.
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; CHECK-REGS-VP: Cost for VF vscale x 16: 21 (Estimated cost per lane: 1.
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; CHECK-REGS-VP: LV: Selecting VF: vscale x 8.
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; CHECK-NOREGS-VP: Cost for VF vscale x 4: 6 (Estimated cost per lane: 1.
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; CHECK-NOREGS-VP: LV(REG): Cost of 6 from 3 spills of Generic::VectorRC
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; CHECK-NOREGS-VP-NEXT: Cost for VF vscale x 8: 20 (Estimated cost per lane: 2.
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; CHECK-NOREGS-VP: LV(REG): Cost of 14 from 7 spills of Generic::VectorRC
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; CHECK-NOREGS-VP-NEXT: Cost for VF vscale x 16: 39 (Estimated cost per lane: 2.
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; CHECK-NOREGS-VP: LV: Selecting VF: vscale x 4.
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.a = getelementptr i32, ptr %a, i64 %iv
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%load.a = load i32, ptr %gep.a, align 4
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%gep.b = getelementptr i8, ptr %b, i64 %iv
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%load.b = load i8, ptr %gep.b, align 1
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%ext.b = zext i8 %load.b to i32
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%add = add i32 %load.a, %ext.b
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store i32 %add, ptr %gep.a, align 4
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%iv.next = add i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 1024
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
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