d8671280d4
After #183080, the canonical IV (not the increment!) can't overflow. So now canonical IVs that are unrolled will have steps that don't overflow, so we can add the nuw flag. This allows us to tighten the VPlanVerifier isKnownMonotonic check by restricting it to adds with nuw.
62 lines
3.1 KiB
LLVM
62 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
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; RUN: opt -passes="loop-vectorize" -mtriple=arm64-apple-macosx -S %s | FileCheck %s
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define i64 @reduction(i64 %arg) #0 {
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; CHECK-LABEL: define i64 @reduction(
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; CHECK-SAME: i64 [[ARG:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4)
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; CHECK-NEXT: [[TMP5]] = or <4 x i32> [[VEC_PHI]], splat (i32 1)
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; CHECK-NEXT: [[TMP1]] = or <4 x i32> [[VEC_PHI2]], splat (i32 1)
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i64> [[STEP_ADD]], splat (i64 4)
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
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; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[BIN_RDX1:%.*]] = or <4 x i32> [[TMP1]], [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX1]])
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 96, %[[SCALAR_PH]] ], [ [[TMP3:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ [[TMP7]], %[[SCALAR_PH]] ], [ [[TMP2:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP2]] = or i32 [[VEC_PHI1]], 1
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; CHECK-NEXT: [[TMP3]] = add nsw i64 [[TMP0]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = mul nsw i64 [[TMP3]], [[ARG]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[TMP3]], 100
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; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[MUL_LCSSA:%.*]] = phi i64 [ [[TMP4]], %[[LOOP]] ]
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; CHECK-NEXT: [[BIN_RDX:%.*]] = phi i32 [ [[TMP2]], %[[LOOP]] ]
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; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[BIN_RDX]] to i64
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; CHECK-NEXT: [[RES:%.*]] = add i64 [[EXT]], [[MUL_LCSSA]]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ]
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%rdx.next = or i32 %rdx, 1
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%iv.next = add nsw i64 %iv, 1
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%mul = mul nsw i64 %iv.next, %arg
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%cmp = icmp ne i64 %iv.next, 100
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br i1 %cmp, label %loop, label %exit
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exit:
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%rdx.next.lcssa = phi i32 [ %rdx.next, %loop ]
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%ext = zext i32 %rdx.next.lcssa to i64
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%res = add i64 %ext, %mul
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ret i64 %res
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}
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