d43213fe80
This reverts commit b0b3e3e1c7f6387eabc2ef9ff1fea311e63a4299. After thinking about this for a bit, I don't think this is correct. vscale being a power-of-2 only guarantees the canonical IV increment overflows to zero, but not overflows in general.
263 lines
15 KiB
LLVM
263 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64-unknown-linux-gnu"
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; Test case for https://github.com/llvm/llvm-project/issues/106417.
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define void @skip_free_iv_truncate(i16 %x, ptr %A) #0 {
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; CHECK-LABEL: define void @skip_free_iv_truncate(
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; CHECK-SAME: i16 [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[X_I32:%.*]] = sext i16 [[X]] to i32
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; CHECK-NEXT: [[X_I64:%.*]] = sext i16 [[X]] to i64
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; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr i8, ptr [[A]], i64 -8
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; CHECK-NEXT: [[SMAX20:%.*]] = call i64 @llvm.smax.i64(i64 [[X_I64]], i64 99)
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[SMAX20]], [[X_I64]]
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; CHECK-NEXT: [[UMIN21:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 1)
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; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[SMAX20]], [[UMIN21]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[X_I64]]
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; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP2]], 3
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; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[UMIN21]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 1
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; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
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; CHECK: [[VECTOR_MEMCHECK]]:
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; CHECK-NEXT: [[TMP31:%.*]] = shl nsw i64 [[X_I64]], 1
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; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP31]]
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; CHECK-NEXT: [[SMAX10:%.*]] = call i64 @llvm.smax.i64(i64 [[X_I64]], i64 99)
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; CHECK-NEXT: [[TMP32:%.*]] = sub i64 [[SMAX10]], [[X_I64]]
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; CHECK-NEXT: [[UMIN11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP32]], i64 1)
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; CHECK-NEXT: [[TMP33:%.*]] = sub i64 [[SMAX10]], [[UMIN11]]
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; CHECK-NEXT: [[TMP34:%.*]] = sub i64 [[TMP33]], [[X_I64]]
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; CHECK-NEXT: [[TMP35:%.*]] = udiv i64 [[TMP34]], 3
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; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[UMIN11]], [[TMP35]]
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; CHECK-NEXT: [[TMP37:%.*]] = mul i64 [[TMP36]], 6
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; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP37]], [[TMP31]]
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; CHECK-NEXT: [[TMP39:%.*]] = add i64 [[TMP38]], 2
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; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP39]]
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; CHECK-NEXT: [[TMP40:%.*]] = shl nsw i64 [[X_I64]], 3
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; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP40]]
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; CHECK-NEXT: [[TMP41:%.*]] = mul i64 [[TMP36]], 24
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; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], [[TMP40]]
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; CHECK-NEXT: [[TMP43:%.*]] = add i64 [[TMP42]], 8
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; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP43]]
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; CHECK-NEXT: [[TMP44:%.*]] = add nsw i64 [[TMP40]], -8
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; CHECK-NEXT: [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP44]]
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; CHECK-NEXT: [[SCEVGEP16:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP42]]
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; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP9]], [[SCEVGEP14]]
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; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP13]], [[SCEVGEP12]]
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; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
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; CHECK-NEXT: [[BOUND017:%.*]] = icmp ult ptr [[SCEVGEP9]], [[SCEVGEP16]]
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; CHECK-NEXT: [[BOUND118:%.*]] = icmp ult ptr [[SCEVGEP15]], [[SCEVGEP12]]
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; CHECK-NEXT: [[FOUND_CONFLICT19:%.*]] = and i1 [[BOUND017]], [[BOUND118]]
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; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT19]]
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; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP53:%.*]] = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()
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; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[X_I64]], i64 0
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; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP55:%.*]] = mul <vscale x 8 x i64> [[TMP53]], splat (i64 3)
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 8 x i64> [[DOTSPLAT]], [[TMP55]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 8 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP5]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true)
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; CHECK-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64
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; CHECK-NEXT: [[TMP58:%.*]] = mul i64 3, [[TMP28]]
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; CHECK-NEXT: [[DOTSPLATINSERT24:%.*]] = insertelement <vscale x 8 x i64> poison, i64 [[TMP58]], i64 0
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; CHECK-NEXT: [[DOTSPLAT25:%.*]] = shufflevector <vscale x 8 x i64> [[DOTSPLATINSERT24]], <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP59:%.*]] = getelementptr i16, ptr [[A]], <vscale x 8 x i64> [[VEC_IND]]
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; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 [[TMP59]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP27]]), !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP28]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 8 x i64> [[VEC_IND]], [[DOTSPLAT25]]
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; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[X_I64]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV_CONV:%.*]] = phi i32 [ [[X_I32]], %[[SCALAR_PH]] ], [ [[TMP64:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_I64:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]
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; CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[GEP_I64]], align 8
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; CHECK-NEXT: [[TMP62:%.*]] = sext i32 [[IV_CONV]] to i64
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; CHECK-NEXT: [[GEP_CONV:%.*]] = getelementptr i64, ptr [[INVARIANT_GEP]], i64 [[TMP62]]
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; CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[GEP_CONV]], align 8
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; CHECK-NEXT: [[GEP_I16:%.*]] = getelementptr i16, ptr [[A]], i64 [[IV]]
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; CHECK-NEXT: store i16 0, ptr [[GEP_I16]], align 2
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 3
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; CHECK-NEXT: [[TMP64]] = trunc i64 [[IV_NEXT]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[IV]], 99
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; CHECK-NEXT: br i1 [[C]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%x.i32 = sext i16 %x to i32
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%x.i64 = sext i16 %x to i64
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%invariant.gep = getelementptr i8, ptr %A, i64 -8
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br label %loop
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loop:
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%iv = phi i64 [ %x.i64, %entry ], [ %iv.next, %loop ]
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%iv.conv = phi i32 [ %x.i32, %entry ], [ %5, %loop ]
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%gep.i64 = getelementptr i64, ptr %A, i64 %iv
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%2 = load i64, ptr %gep.i64, align 8
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%3 = sext i32 %iv.conv to i64
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%gep.conv = getelementptr i64, ptr %invariant.gep, i64 %3
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%4 = load i64, ptr %gep.conv, align 8
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%gep.i16 = getelementptr i16, ptr %A, i64 %iv
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store i16 0, ptr %gep.i16, align 2
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%iv.next = add i64 %iv, 3
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%5 = trunc i64 %iv.next to i32
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%c = icmp slt i64 %iv, 99
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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define void @test_3_inductions(ptr noalias %dst, ptr noalias %src, i64 %n) #1 {
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; CHECK-LABEL: define void @test_3_inductions(
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; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[DST]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32()
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; CHECK-NEXT: [[TMP2:%.*]] = mul <vscale x 2 x i32> [[TMP1]], splat (i32 2)
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i32> splat (i32 1), [[TMP2]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <vscale x 2 x i32> [ [[TMP2]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT4:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], 1
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[TMP4]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT2]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = or <vscale x 2 x i32> [[VEC_IND1]], [[VEC_IND]]
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; CHECK-NEXT: [[TMP6:%.*]] = sext <vscale x 2 x i32> [[TMP5]] to <vscale x 2 x i64>
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[SRC]], <vscale x 2 x i64> [[TMP6]]
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; CHECK-NEXT: call void @llvm.vp.scatter.nxv2p0.nxv2p0(<vscale x 2 x ptr> [[TMP7]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP3]])
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT3]]
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; CHECK-NEXT: [[VEC_IND_NEXT4]] = add <vscale x 2 x i32> [[VEC_IND1]], [[BROADCAST_SPLAT3]]
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv.0 = phi i32 [ 1, %entry ], [ %iv.0.next, %loop ]
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%iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ]
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%iv.or = or i32 %iv.2, %iv.0
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%iv.or.ext = sext i32 %iv.or to i64
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%gep.src = getelementptr i8, ptr %src, i64 %iv.or.ext
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store ptr %gep.src, ptr %dst, align 8
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%iv.0.next = add i32 %iv.0, 2
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%iv.1.next = add i64 %iv.1, 1
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%iv.2.next = add i32 %iv.2, 2
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%ec = icmp eq i64 %iv.1, %n
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @redundant_iv_trunc_for_cse(ptr noalias %src, ptr noalias %dst, i64 %n) #0 {
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; CHECK-LABEL: define void @redundant_iv_trunc_for_cse(
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; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i32> [ [[TMP1]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <vscale x 4 x i32> [ [[TMP1]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP0]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[TMP3]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[EVL_BASED_IV]]
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; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP4]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP3]])
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <vscale x 4 x i32> [[VP_OP_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = shl <vscale x 4 x i32> [[VEC_IND1]], splat (i32 16)
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <vscale x 4 x i1> [[TMP5]], <vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[VEC_IND]]
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; CHECK-NEXT: [[TMP7:%.*]] = trunc <vscale x 4 x i32> [[PREDPHI]] to <vscale x 4 x i8>
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[EVL_BASED_IV]]
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; CHECK-NEXT: call void @llvm.vp.store.nxv4i8.p0(<vscale x 4 x i8> [[TMP7]], ptr align 1 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP3]])
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; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP9]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <vscale x 4 x i32> [[VEC_IND1]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%gep.src = getelementptr inbounds i32, ptr %src, i64 %iv
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%l = load i32, ptr %gep.src
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%c.0 = icmp eq i32 %l, 0
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%trunc.iv = trunc i64 %iv to i32
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br i1 %c.0, label %then, label %loop.latch
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then:
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%trunc.iv.2 = trunc i64 %iv to i32
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%shl.iv = shl i32 %trunc.iv.2, 16
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br label %loop.latch
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loop.latch:
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%p = phi i32 [ %shl.iv, %then ], [ %trunc.iv, %loop.header ]
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%trunc.p = trunc i32 %p to i8
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%gep.dst = getelementptr inbounds i8, ptr %dst, i64 %iv
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store i8 %trunc.p, ptr %gep.dst, align 1
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv, %n
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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attributes #0 = { "target-features"="+64bit,+v,+zvl256b" }
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attributes #1 = { "target-cpu"="sifive-p670" }
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;.
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; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
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; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
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; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}
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; CHECK: [[META3]] = !{[[META4:![0-9]+]], [[META5:![0-9]+]]}
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; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}
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; CHECK: [[META5]] = distinct !{[[META5]], [[META2]]}
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; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META8:![0-9]+]]}
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; CHECK: [[META7]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META8]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META7]]}
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; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META7]], [[META8]]}
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; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META7]], [[META8]]}
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;.
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