bf46a95f2c
Fixes #186005 On RV32 with zve32x, i.e. no legal 64 bit types either scalar or vector, @llvm.cttz.elts.i64 cannot be lowered and so returns an illegal cost for scalable VFs. However VPInstruction::FirstActiveLane and VPInstruction::LastActiveLane always use a hardcoded i64 type. This causes a legacy/VPlan cost model mismatch in the live-out.ll test, and in early-exit-live-out.ll prevents the scalable VF from being chosen. This PR teaches the two VPInstructions to use the target's index type, i.e. the width of a pointer in the default address space, so it will generate a 32 bit cttz.elts on RV32. This should be large enough to hold the maximum number of elements in a vector, as if the vector was any bigger it would imply it isn't accessible by memory. I considered using the canonical IV type but I don't think that will work since the canonical IV can be i64 on RV32, and it causes regressions due to extra zexting on 64-bit targets with a 32-bit IV.
98 lines
5.5 KiB
LLVM
98 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
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; RUN: opt < %s -S -p loop-vectorize -mtriple riscv64 -mattr=+v | FileCheck %s --check-prefix=RV64
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; RUN: opt < %s -S -p loop-vectorize -mtriple riscv32 -mattr=+v | FileCheck %s --check-prefix=RV32
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; RUN: opt < %s -S -p loop-vectorize -mtriple riscv32 -mattr=+zve32x,+zvl128b | FileCheck %s --check-prefix=ZVE32X
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; Make sure that we generate a VPInstruction::LastActiveLane that matches the
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; targets index type, i.e. i64 on RV64 and i32 on RV32. Otherwise on rv32 with
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; zve32x we return an invalid cost for cttz.elts with scalable VFs.
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define i32 @live_out(ptr %p, i64 %n) {
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; RV64-LABEL: define i32 @live_out(
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; RV64-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; RV64-NEXT: [[ENTRY:.*:]]
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; RV64-NEXT: br label %[[VECTOR_PH:.*]]
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; RV64: [[VECTOR_PH]]:
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; RV64-NEXT: br label %[[VECTOR_BODY:.*]]
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; RV64: [[VECTOR_BODY]]:
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; RV64-NEXT: [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; RV64-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
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; RV64-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
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; RV64-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
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; RV64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
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; RV64-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
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; RV64-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
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; RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; RV64-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; RV64: [[MIDDLE_BLOCK]]:
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; RV64-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], 1
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; RV64-NEXT: [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i64 [[TMP4]]
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; RV64-NEXT: br label %[[EXIT:.*]]
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; RV64: [[EXIT]]:
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; RV64-NEXT: ret i32 [[TMP5]]
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;
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; RV32-LABEL: define i32 @live_out(
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; RV32-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; RV32-NEXT: [[ENTRY:.*:]]
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; RV32-NEXT: br label %[[VECTOR_PH:.*]]
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; RV32: [[VECTOR_PH]]:
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; RV32-NEXT: br label %[[VECTOR_BODY:.*]]
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; RV32: [[VECTOR_BODY]]:
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; RV32-NEXT: [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; RV32-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
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; RV32-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
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; RV32-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
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; RV32-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
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; RV32-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
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; RV32-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
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; RV32-NEXT: [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; RV32-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; RV32: [[MIDDLE_BLOCK]]:
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; RV32-NEXT: [[TMP4:%.*]] = sub i32 [[TMP0]], 1
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; RV32-NEXT: [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i32 [[TMP4]]
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; RV32-NEXT: br label %[[EXIT:.*]]
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; RV32: [[EXIT]]:
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; RV32-NEXT: ret i32 [[TMP5]]
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;
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; ZVE32X-LABEL: define i32 @live_out(
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; ZVE32X-SAME: ptr [[P:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; ZVE32X-NEXT: [[ENTRY:.*:]]
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; ZVE32X-NEXT: br label %[[VECTOR_PH:.*]]
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; ZVE32X: [[VECTOR_PH]]:
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; ZVE32X-NEXT: br label %[[VECTOR_BODY:.*]]
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; ZVE32X: [[VECTOR_BODY]]:
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; ZVE32X-NEXT: [[CURRENT_ITERATION_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; ZVE32X-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; ZVE32X-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
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; ZVE32X-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[P]], i64 [[CURRENT_ITERATION_IV]]
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; ZVE32X-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP1]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP0]])
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; ZVE32X-NEXT: [[TMP2:%.*]] = zext i32 [[TMP0]] to i64
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; ZVE32X-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP2]], [[CURRENT_ITERATION_IV]]
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; ZVE32X-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]]
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; ZVE32X-NEXT: [[TMP3:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; ZVE32X-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; ZVE32X: [[MIDDLE_BLOCK]]:
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; ZVE32X-NEXT: [[TMP4:%.*]] = sub i32 [[TMP0]], 1
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; ZVE32X-NEXT: [[TMP5:%.*]] = extractelement <vscale x 4 x i32> [[VP_OP_LOAD]], i32 [[TMP4]]
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; ZVE32X-NEXT: br label %[[EXIT:.*]]
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; ZVE32X: [[EXIT]]:
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; ZVE32X-NEXT: ret i32 [[TMP5]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [0, %entry], [%iv.next, %loop]
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%gep = getelementptr i32, ptr %p, i64 %iv
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%ld = load i32, ptr %gep
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv.next, %n
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br i1 %ec, label %exit, label %loop
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exit:
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%ret = phi i32 [ %ld, %loop ]
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ret i32 %ret
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}
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