7074471593
We have been tracking the performance of EVL tail folding in the loop vectorizer on RISC-V for a while now, and after much hard work from various contributors we think it should be generally profitable to enable by default now. With tail folding there is a 21% improvement on 525.x264_r on SPEC CPU 2017 on the BPI-F3 (-march=rva22u64_v -O3 -flto), as well as a 30% geomean codesize reduction on SPEC and TSVC, with no significant regressions detected. Now that we are early into the LLVM 22.x development cycle it seems like a good time to enable it to catch any issues. There are still more EVL related items of work being tracked in #123069, which should continue to improve performance.
69 lines
2.4 KiB
LLVM
69 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=riscv64 -mattr=+zve32x -passes=loop-vectorize < %s | FileCheck %s
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define void @small_trip_count_min_vlen_128(ptr nocapture %a) nounwind vscale_range(4,1024) {
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; CHECK-LABEL: @small_trip_count_min_vlen_128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP1:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP1]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i32 [[IV]]
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; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[V]], 1
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; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 3
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; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[LOOP1]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%gep = getelementptr inbounds i32, ptr %a, i32 %iv
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%v = load i32, ptr %gep, align 4
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%add = add nsw i32 %v, 1
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store i32 %add, ptr %gep, align 4
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%iv.next = add i32 %iv, 1
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%cond = icmp eq i32 %iv, 3
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br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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define void @small_trip_count_min_vlen_32(ptr nocapture %a) nounwind vscale_range(1,1024) {
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; CHECK-LABEL: @small_trip_count_min_vlen_32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP1:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP1]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i32 [[IV]]
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; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[GEP]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[V]], 1
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; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 3
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; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[LOOP1]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%gep = getelementptr inbounds i32, ptr %a, i32 %iv
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%v = load i32, ptr %gep, align 4
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%add = add nsw i32 %v, 1
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store i32 %add, ptr %gep, align 4
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%iv.next = add i32 %iv, 1
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%cond = icmp eq i32 %iv, 3
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br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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