958cec0ab1
There were 5 X86 loop vectoriser tests that were piping the output from opt into llc. I think in the directory test/Transforms/LoopVectorize we should only be testing the output from the loop vectoriser pass. Any codegen tests should live in test/CodeGen/X86 instead. avx512.ll: it looks like we were really just testing that we generate the right vector length. fp32_to_uint32-cost-model.ll/fp64_to_uint32-cost-model.ll: the tests only seem to care that we're not scalarising the fptoui, so I've modified the test to check for vector ops. I've assumed there are already codegen tests for fptoui vector operations. vectorization-remarks-loopid-dbg.ll: i've copied this test to CodeGen/X86/vectorization-remarks-loopid-dbg.ll for the llc RUN line variant vectorization-remarks.ll: seems to test the same thing as vectorization-remarks-loopid-dbg.ll
113 lines
4.0 KiB
LLVM
113 lines
4.0 KiB
LLVM
; RUN: opt -mattr=+avx512f -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-NO-PREFER
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; RUN: opt -mattr=+avx512vl,+prefer-256-bit -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-AVX256
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.9.0"
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; Verify that we generate 512-bit wide vectors for a basic integer memset
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; loop.
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; CHECK-NO-PREFER-LABEL: @f(
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; CHECK-NO-PREFER: vector.body:
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; CHECK-NO-PREFER: store <16 x i32>
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; CHECK-NO-PREFER: vec.epilog.vector.body:
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; CHECK-NO-PREFER: store <8 x i32>
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; Verify that we don't generate 512-bit wide vectors when subtarget feature says not to
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; CHECK-PREFER-AVX256-LABEL: @f(
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; CHECK-PREFER-AVX256: vector.body:
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; CHECK-PREFER-AVX256: store <8 x i32>
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; CHECK-PREFER-AVX256: vec.epilog.vector.body:
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; CHECK-PREFER-AVX256: store <4 x i32>
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define void @f(ptr %a, i32 %n) {
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body.preheader, label %for.end
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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store i32 %n, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end.loopexit, label %for.body
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for.end.loopexit: ; preds = %for.body
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br label %for.end
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for.end: ; preds = %for.end.loopexit, %entry
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ret void
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}
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; Verify that the "prefer-vector-width=256" attribute prevents the use of 512-bit
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; vectors
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; CHECK-LABEL: @g(
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; CHECK: vector.body:
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; CHECK: store <8 x i32>
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; CHECK: vec.epilog.vector.body:
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; CHECK: store <4 x i32>
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define void @g(ptr %a, i32 %n) "prefer-vector-width"="256" {
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body.preheader, label %for.end
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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store i32 %n, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end.loopexit, label %for.body
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for.end.loopexit: ; preds = %for.body
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br label %for.end
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for.end: ; preds = %for.end.loopexit, %entry
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ret void
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}
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; Verify that the "prefer-vector-width=512" attribute override the subtarget
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; vectors
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; CHECK-LABEL: @h(
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; CHECK: vector.body:
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; CHECK: store <16 x i32>
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; CHECK: vec.epilog.vector.body:
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; CHECK: store <8 x i32>
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define void @h(ptr %a, i32 %n) "prefer-vector-width"="512" {
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entry:
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%cmp4 = icmp sgt i32 %n, 0
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br i1 %cmp4, label %for.body.preheader, label %for.end
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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store i32 %n, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end.loopexit, label %for.body
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for.end.loopexit: ; preds = %for.body
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br label %for.end
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for.end: ; preds = %for.end.loopexit, %entry
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ret void
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}
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