d316fb0797
Extend replicateByVF to also handle VPScalarIVStepsRecipe. To do so, the patch adds a new lane operand to VPScalarIVStepsRecipe, which is only added when replicating. This enables removing a number of lane 0 computations. The lane operand will also be used to explicitly replicate replicate regions in a follow-up. Depends on https://github.com/llvm/llvm-project/pull/169796 Depends on https://github.com/llvm/llvm-project/pull/170906 PR: https://github.com/llvm/llvm-project/pull/170053
83 lines
4.2 KiB
LLVM
83 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1-p:16:16:16:16"
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declare void @init(ptr nocapture nofree)
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; Test where offset relative to alloca is negative and we shouldn't
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; treat predicated loads as being always dereferenceable.
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define i8 @test_negative_off(i16 %len, ptr %test_base) {
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; CHECK-LABEL: @test_negative_off(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [64638 x i8], align 1
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; CHECK-NEXT: call void @init(ptr [[ALLOCA]])
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; CHECK-NEXT: br label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_LOAD_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i8> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP18:%.*]], [[PRED_LOAD_CONTINUE2]] ]
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; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i16
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 -1000, [[DOTCAST]]
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; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i16> poison, i16 [[OFFSET_IDX]], i32 0
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; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i16> [[TMP8]], i16 [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE:%.*]], i16 [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i1, ptr [[TEST_BASE]], i16 [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = load i1, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[TMP5:%.*]] = load i1, ptr [[TMP3]], align 1
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i1> poison, i1 [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i1> [[TMP6]], i1 [[TMP5]], i32 1
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; CHECK-NEXT: br i1 [[TMP4]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
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; CHECK: pred.load.if:
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[ALLOCA]], i16 [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 1
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; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i8> poison, i8 [[TMP10]], i32 0
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; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]]
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; CHECK: pred.load.continue:
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; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i8> [ poison, [[VECTOR_BODY]] ], [ [[TMP11]], [[PRED_LOAD_IF]] ]
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; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_LOAD_IF1:%.*]], label [[PRED_LOAD_CONTINUE2]]
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; CHECK: pred.load.if1:
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[ALLOCA]], i16 [[TMP1]]
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; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP14]], align 1
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; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x i8> [[TMP12]], i8 [[TMP15]], i32 1
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; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]]
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; CHECK: pred.load.continue2:
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; CHECK-NEXT: [[TMP17:%.*]] = phi <2 x i8> [ [[TMP12]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP16]], [[PRED_LOAD_IF1]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP7]], <2 x i8> [[TMP17]], <2 x i8> zeroinitializer
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; CHECK-NEXT: [[TMP18]] = add <2 x i8> [[VEC_PHI]], [[PREDPHI]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP20:%.*]] = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> [[TMP18]])
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; CHECK-NEXT: br label [[LATCH:%.*]]
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; CHECK: loop_exit:
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; CHECK-NEXT: ret i8 [[TMP20]]
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;
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entry:
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%alloca = alloca [64638 x i8]
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call void @init(ptr %alloca)
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br label %loop
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loop:
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%iv = phi i16 [ -1000, %entry ], [ %iv.next, %latch ]
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%accum = phi i8 [ 0, %entry ], [ %accum.next, %latch ]
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%iv.next = add i16 %iv, 1
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%test_addr = getelementptr inbounds i1, ptr %test_base, i16 %iv
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%earlycnd = load i1, ptr %test_addr
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br i1 %earlycnd, label %pred, label %latch
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pred:
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%addr = getelementptr i8, ptr %alloca, i16 %iv
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%val = load i8, ptr %addr
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br label %latch
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latch:
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%val.phi = phi i8 [ 0, %loop ], [ %val, %pred ]
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%accum.next = add i8 %accum, %val.phi
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%exit = icmp ugt i16 %iv, -990
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br i1 %exit, label %loop_exit, label %loop
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loop_exit:
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ret i8 %accum.next
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}
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