9e4dddcc12
Phi folding is suppressed over binary operation inputs in order to avoid interfering with switch formation. After #183692, code (for example, Rust's ASCII character classification) may get an `or` hoisted up into it, which suppresses `foldTwoEntryPHINode`. This then produces branching code where previously we generated straightline code. To maintain switch formation while preventing any binops from breaking phi folding, restrict the scenario in which Phi folding is suppressed to binops of *equality* ops. This should mesh with switch statements, which require an explicit list of values, while not breaking optimization over > / < etc. which would never have been promoted to switches in the first place. Fixes: rust-lang/rust#153504
402 lines
16 KiB
LLVM
402 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O2 -S -mattr=avx < %s | FileCheck %s
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; RUN: opt -passes="default<O2>" -S -mattr=avx < %s | FileCheck %s
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target triple = "x86_64--"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i32 @ext_ext_or_reduction_v4i32(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @ext_ext_or_reduction_v4i32(
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; CHECK-NEXT: [[Z:%.*]] = and <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[Z]])
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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%z = and <4 x i32> %x, %y
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%z0 = extractelement <4 x i32> %z, i32 0
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%z1 = extractelement <4 x i32> %z, i32 1
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%z01 = or i32 %z0, %z1
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%z2 = extractelement <4 x i32> %z, i32 2
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%z012 = or i32 %z01, %z2
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%z3 = extractelement <4 x i32> %z, i32 3
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%z0123 = or i32 %z3, %z012
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ret i32 %z0123
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}
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define i32 @ext_ext_partial_add_reduction_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: @ext_ext_partial_add_reduction_v4i32(
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]]
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; CHECK-NEXT: [[SHIFT1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> <i32 2, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[SHIFT1]]
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; CHECK-NEXT: [[X210:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
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; CHECK-NEXT: ret i32 [[X210]]
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;
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%x0 = extractelement <4 x i32> %x, i32 0
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%x1 = extractelement <4 x i32> %x, i32 1
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%x10 = add i32 %x1, %x0
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%x2 = extractelement <4 x i32> %x, i32 2
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%x210 = add i32 %x2, %x10
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ret i32 %x210
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}
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define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @ext_ext_partial_add_reduction_and_extra_add_v4i32(
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%y0 = extractelement <4 x i32> %y, i32 0
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%y1 = extractelement <4 x i32> %y, i32 1
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%y10 = add i32 %y1, %y0
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%y2 = extractelement <4 x i32> %y, i32 2
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%y210 = add i32 %y2, %y10
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%x2 = extractelement <4 x i32> %x, i32 2
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%x2y210 = add i32 %x2, %y210
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ret i32 %x2y210
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}
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; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=43953
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; We want to end up with a single reduction on the next 4 tests.
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define i32 @TestVectorsEqual(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqual(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP2]], i1 true)
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; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
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; CHECK-NEXT: [[CMP5_NOT:%.*]] = icmp sle i32 [[TMP4]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5_NOT]] to i32
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; CHECK-NEXT: ret i32 [[COND6]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom
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%0 = load i32, ptr %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1
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%1 = load i32, ptr %arrayidx2, align 4
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%sub = sub nsw i32 %0, %1
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%cmp3 = icmp sge i32 %sub, 0
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br i1 %cmp3, label %cond.true, label %cond.false
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cond.true:
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br label %cond.end
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cond.false:
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%sub4 = sub nsw i32 0, %sub
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %sub, %cond.true ], [ %sub4, %cond.false ]
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%add = add nsw i32 %sum.0, %cond
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp5 = icmp sle i32 %sum.0, %Tolerance
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%2 = zext i1 %cmp5 to i64
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%cond6 = select i1 %cmp5, i32 1, i32 0
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ret i32 %cond6
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}
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define i32 @TestVectorsEqual_alt(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqual_alt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[ADD_3:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
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; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp ule i32 [[ADD_3]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3_NOT]] to i32
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom
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%0 = load i32, ptr %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1
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%1 = load i32, ptr %arrayidx2, align 4
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%sub = sub i32 %0, %1
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%add = add i32 %sum.0, %sub
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp3 = icmp ule i32 %sum.0, %Tolerance
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%2 = zext i1 %cmp3 to i64
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%cond = select i1 %cmp3, i32 1, i32 0
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ret i32 %cond
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}
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define i32 @TestVectorsEqualFP(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqualFP(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
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; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP3]])
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; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ole float [[TMP4]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32
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; CHECK-NEXT: ret i32 [[COND5]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom
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%0 = load float, ptr %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1
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%1 = load float, ptr %arrayidx2, align 4
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%sub = fsub fast float %0, %1
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%cmp3 = fcmp fast oge float %sub, 0.000000e+00
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br i1 %cmp3, label %cond.true, label %cond.false
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cond.true:
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br label %cond.end
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cond.false:
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%fneg = fneg fast float %sub
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br label %cond.end
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cond.end:
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%cond = phi fast float [ %sub, %cond.true ], [ %fneg, %cond.false ]
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%add = fadd fast float %sum.0, %cond
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp4 = fcmp fast ole float %sum.0, %Tolerance
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%2 = zext i1 %cmp4 to i64
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%cond5 = select i1 %cmp4, i32 1, i32 0
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ret i32 %cond5
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}
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define i32 @TestVectorsEqualFP_alt(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {
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; CHECK-LABEL: @TestVectorsEqualFP_alt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = fsub fast <4 x float> [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[TMP2]])
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; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP3]], [[TOLERANCE:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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br label %for.cond
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for.cond:
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%sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
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%Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp = icmp slt i32 %Component.0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup:
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br label %for.end
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for.body:
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%idxprom = sext i32 %Component.0 to i64
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%arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom
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%0 = load float, ptr %arrayidx, align 4
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%idxprom1 = sext i32 %Component.0 to i64
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%arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1
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%1 = load float, ptr %arrayidx2, align 4
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%sub = fsub fast float %0, %1
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%add = fadd fast float %sum.0, %sub
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br label %for.inc
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for.inc:
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%inc = add nsw i32 %Component.0, 1
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br label %for.cond
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for.end:
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%cmp3 = fcmp fast ole float %sum.0, %Tolerance
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%2 = zext i1 %cmp3 to i64
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%cond = select i1 %cmp3, i32 1, i32 0
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ret i32 %cond
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}
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; PR43745 - https://bugs.llvm.org/show_bug.cgi?id=43745
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; FIXME: this should be vectorized
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define i1 @cmp_lt_gt(double %a, double %b, double %c) {
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; CHECK-LABEL: @cmp_lt_gt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]
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; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
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; CHECK-NEXT: [[C:%.*]] = fsub double [[FNEG]], [[C1:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = fsub double [[C1]], [[B]]
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[ADD]], i64 0
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C]], i64 1
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[MUL]], i64 0
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP7:%.*]] = fdiv <2 x double> [[TMP3]], [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = fcmp uge <2 x double> [[TMP7]], splat (double 0x3EB0C6F7A0B5ED8D)
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison>
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; CHECK-NEXT: [[OR_COND:%.*]] = or <2 x i1> [[TMP8]], [[SHIFT]]
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; CHECK-NEXT: [[TMP10:%.*]] = fcmp ule <2 x double> [[TMP7]], splat (double 1.000000e+00)
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; CHECK-NEXT: [[SHIFT2:%.*]] = shufflevector <2 x i1> [[TMP10]], <2 x i1> poison, <2 x i32> <i32 1, i32 poison>
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; CHECK-NEXT: [[TMP11:%.*]] = or <2 x i1> [[TMP10]], [[SHIFT2]]
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; CHECK-NEXT: [[OR_COND1_NOT:%.*]] = and <2 x i1> [[OR_COND]], [[TMP11]]
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; CHECK-NEXT: [[RETVAL_0:%.*]] = extractelement <2 x i1> [[OR_COND1_NOT]], i64 0
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; CHECK-NEXT: ret i1 [[RETVAL_0]]
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;
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entry:
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%fneg = fneg double %b
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%add = fadd double %fneg, %c
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%mul = fmul double 2.0, %a
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%div = fdiv double %add, %mul
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%fneg1 = fneg double %b
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%sub = fsub double %fneg1, %c
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%mul2 = fmul double 2.0, %a
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%div3 = fdiv double %sub, %mul2
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%cmp = fcmp olt double %div, 0x3EB0C6F7A0B5ED8D
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br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
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land.lhs.true:
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%cmp4 = fcmp olt double %div3, 0x3EB0C6F7A0B5ED8D
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br i1 %cmp4, label %if.then, label %lor.lhs.false
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lor.lhs.false:
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%cmp5 = fcmp ogt double %div, 1.0
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br i1 %cmp5, label %land.lhs.true6, label %if.end
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land.lhs.true6:
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%cmp7 = fcmp ogt double %div3, 1.0
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br i1 %cmp7, label %if.then, label %if.end
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if.then:
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br label %cleanup
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if.end:
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br label %cleanup
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cleanup:
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%retval.0 = phi i1 [ false, %if.then ], [ true, %if.end ]
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ret i1 %retval.0
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}
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define i8 @masked_min_reduction(ptr %data, ptr %mask) {
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; CHECK-LABEL: @masked_min_reduction(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP18:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <32 x i8> [ splat (i8 -1), [[ENTRY]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[DATA:%.*]] = getelementptr i8, ptr [[DATA1:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[DATA]], i64 32
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DATA]], i64 64
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DATA]], i64 96
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[DATA]], align 1
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; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP1]], align 1
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; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <32 x i8>, ptr [[TMP3]], align 1
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[MASK:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP7]], i64 32
|
|
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP7]], i64 64
|
|
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP7]], i64 96
|
|
; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <32 x i8>, ptr [[TMP7]], align 1
|
|
; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <32 x i8>, ptr [[TMP5]], align 1
|
|
; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <32 x i8>, ptr [[TMP6]], align 1
|
|
; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <32 x i8>, ptr [[TMP22]], align 1
|
|
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD7]], zeroinitializer
|
|
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD8]], zeroinitializer
|
|
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD9]], zeroinitializer
|
|
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <32 x i8> [[WIDE_LOAD10]], zeroinitializer
|
|
; CHECK-NEXT: [[TMP12:%.*]] = select <32 x i1> [[TMP8]], <32 x i8> [[WIDE_LOAD]], <32 x i8> splat (i8 -1)
|
|
; CHECK-NEXT: [[TMP13:%.*]] = select <32 x i1> [[TMP9]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> splat (i8 -1)
|
|
; CHECK-NEXT: [[TMP14:%.*]] = select <32 x i1> [[TMP10]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> splat (i8 -1)
|
|
; CHECK-NEXT: [[TMP15:%.*]] = select <32 x i1> [[TMP11]], <32 x i8> [[WIDE_LOAD6]], <32 x i8> splat (i8 -1)
|
|
; CHECK-NEXT: [[TMP16]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI]], <32 x i8> [[TMP12]])
|
|
; CHECK-NEXT: [[TMP17]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI1]], <32 x i8> [[TMP13]])
|
|
; CHECK-NEXT: [[TMP18]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI2]], <32 x i8> [[TMP14]])
|
|
; CHECK-NEXT: [[TMP19]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[VEC_PHI3]], <32 x i8> [[TMP15]])
|
|
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128
|
|
; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
|
|
; CHECK-NEXT: br i1 [[TMP20]], label [[EXIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: [[RDX_MINMAX:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[TMP16]], <32 x i8> [[TMP17]])
|
|
; CHECK-NEXT: [[RDX_MINMAX11:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[RDX_MINMAX]], <32 x i8> [[TMP18]])
|
|
; CHECK-NEXT: [[RDX_MINMAX12:%.*]] = tail call <32 x i8> @llvm.umin.v32i8(<32 x i8> [[RDX_MINMAX11]], <32 x i8> [[TMP19]])
|
|
; CHECK-NEXT: [[TMP21:%.*]] = tail call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> [[RDX_MINMAX12]])
|
|
; CHECK-NEXT: ret i8 [[TMP21]]
|
|
;
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%i = phi i64 [ 0, %entry ], [ %next, %loop ]
|
|
%acc = phi i8 [ 255, %entry ], [ %acc_next, %loop ]
|
|
|
|
%ptr_i = getelementptr i8, ptr %data, i64 %i
|
|
%val = load i8, ptr %ptr_i, align 1
|
|
|
|
%mask_ptr = getelementptr i8, ptr %mask, i64 %i
|
|
%m = load i8, ptr %mask_ptr, align 1
|
|
%cond = icmp eq i8 %m, 0
|
|
|
|
; Use select to implement masking
|
|
%masked_val = select i1 %cond, i8 %val, i8 255
|
|
|
|
; min reduction
|
|
%acc_next = call i8 @llvm.umin.i8(i8 %acc, i8 %masked_val)
|
|
|
|
%next = add i64 %i, 1
|
|
%cmp = icmp ult i64 %next, 1024
|
|
br i1 %cmp, label %loop, label %exit
|
|
|
|
exit:
|
|
ret i8 %acc_next
|
|
}
|