2bb0fa46a8
If the instructions state is alternate and/or contains non-directly matching instructions, need to check if it is better to represent such operations as non-alternate with copyables. To do this, we need to compare operands between the instructions in their different representations and choose the best one for optimal vectorization. Reviewers: RKSimon, hiraditya Pull Request: https://github.com/llvm/llvm-project/pull/183777
41 lines
2.1 KiB
LLVM
41 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=X86 %}
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; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=AARCH64 %}
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define i32 @test() {
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; X86-LABEL: @test(
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; X86-NEXT: bb:
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; X86-NEXT: [[TMP0:%.*]] = shufflevector <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; X86-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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; X86-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer
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; X86-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP4]])
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; X86-NEXT: ret i32 [[TMP5]]
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;
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; AARCH64-LABEL: @test(
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; AARCH64-NEXT: bb:
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; AARCH64-NEXT: [[TMP0:%.*]] = shufflevector <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; AARCH64-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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; AARCH64-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer
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; AARCH64-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]])
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; AARCH64-NEXT: ret i32 [[TMP3]]
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;
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bb:
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%0 = shufflevector <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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%1 = extractelement <4 x i32> %0, i32 3
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%2 = extractelement <4 x i32> %0, i32 2
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%3 = extractelement <4 x i32> %0, i32 1
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%4 = extractelement <4 x i32> %0, i32 0
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%inst514 = or i32 %4, 0
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%inst494 = or i32 %3, 0
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%inst474 = or i32 %2, 0
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%inst454 = or i32 %1, 0
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%inst458 = add i32 %1, %inst454
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%inst477 = add i32 %inst458, %2
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%inst478 = add i32 %inst477, %inst474
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%inst497 = add i32 %inst478, %3
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%inst498 = add i32 %inst497, %inst494
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%inst517 = add i32 %inst498, %4
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%inst518 = add i32 %inst517, %inst514
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ret i32 %inst518
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}
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