Yingwei Zheng 650026897c

[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364) ...

This patch lowers `sdiv x, +/-2**k` to `add + select + shift` when the
short forward branch optimization is enabled. The latter inst seq
performs faster than the seq generated by target-independent
DAGCombiner. This algorithm is described in ***Hacker's Delight***.

This patch also removes duplicate logic in the X86 and AArch64 backend.
But we cannot do this for the PowerPC backend since it generates a
special instruction `addze`.

2023-11-10 21:38:47 +08:00

..

CMakeLists.txt

Split out CodeGenTypes from CodeGen for LLT/MVT

2023-05-03 00:13:20 +09:00

DAGCombiner.cpp

Revert "[DAGCombiner] Transform (icmp eq/ne (and X,C0),(shift X,C1)) to use rotate or to getter constants." due to a miscompile (#71598)

2023-11-08 15:07:12 +01:00

FastISel.cpp

[FastISel][DebugInfo] Handle dbg.value targeting allocas (#67187)

2023-10-02 07:10:11 -07:00

FunctionLoweringInfo.cpp

[1/11][IR] Permit load/store/alloca for struct of the same scalable vector type

2023-05-19 09:39:36 -07:00

InstrEmitter.cpp

[InlineAsm] refactor InlineAsm class NFC (#65649)

2023-09-11 09:27:37 -07:00

InstrEmitter.h

[DebugInfo] Store instr-ref mode of MachineFunction in member

2023-01-20 14:47:11 +00:00

LegalizeDAG.cpp

[SDAG] Avoid use of ConstantExpr::getFPTrunc() (NFC)

2023-11-06 15:55:23 +01:00

LegalizeFloatTypes.cpp

[SelectionDAG] Adjust placement of blank lines in debug output. NFC (#70969)

2023-11-02 09:35:04 -07:00

LegalizeIntegerTypes.cpp

[SelectionDAG] Adjust placement of blank lines in debug output. NFC (#70969)

2023-11-02 09:35:04 -07:00

LegalizeTypes.cpp

[SelectionDAG] Adjust placement of blank lines in debug output. NFC (#70969)

2023-11-02 09:35:04 -07:00

LegalizeTypes.h

[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)

2023-11-05 22:39:27 -08:00

LegalizeTypesGeneric.cpp

[LegalizeType][X86] Support WidenVecRes_AssertZext and SplitVecRes_AssertZext for ISD::AssertZext during LegalizeType procedure

2023-05-24 10:17:08 +08:00

LegalizeVectorOps.cpp

[RISCV] Support Strict FP arithmetic Op when only have Zvfhmin (#68867)

2023-11-09 09:55:48 +08:00

LegalizeVectorTypes.cpp

[VP][RISCV] Add llvm.experimental.vp.reverse. (#70405)

2023-11-05 22:39:27 -08:00

ResourcePriorityQueue.cpp

…

ScheduleDAGFast.cpp

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

2023-09-14 14:10:14 -07:00

ScheduleDAGRRList.cpp

[X86]Remove X86-specific dead code in ScheduleDAGRRList.cpp (#67629)

2023-09-30 15:49:37 +08:00

ScheduleDAGSDNodes.cpp

Clean come dead code

2023-04-23 20:46:34 -04:00

ScheduleDAGSDNodes.h

Restore CodeGen/MachineValueType.h from Support

2023-05-03 00:13:20 +09:00

ScheduleDAGVLIW.cpp

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

2023-09-14 14:10:14 -07:00

SDNodeDbgValue.h

[DebugInfo] Remove dbg.addr from CodeGen

2023-03-02 09:29:43 +00:00

SelectionDAG.cpp

[SelectionDAG] Add initial support for nneg flag on ISD::ZERO_EXTEND. (#70872)

2023-11-03 11:15:08 -07:00

SelectionDAGAddressAnalysis.cpp

[X86] Fix aliasing check between TargetFrameIndex and FrameIndex

2023-08-17 10:48:08 +01:00

SelectionDAGBuilder.cpp

[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)

2023-11-06 12:30:07 +01:00

SelectionDAGBuilder.h

[StatepointLowering] Take return attributes of gc.result into account (#68439)

2023-10-14 18:38:18 +02:00

SelectionDAGDumper.cpp

[SelectionDAG] Add initial support for nneg flag on ISD::ZERO_EXTEND. (#70872)

2023-11-03 11:15:08 -07:00

SelectionDAGISel.cpp

[SelectionDAG] Adjust placement of blank lines in debug output. NFC (#70969)

2023-11-02 09:35:04 -07:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[StatepointLowering] Take return attributes of gc.result into account (#68439)

2023-10-14 18:38:18 +02:00

StatepointLowering.h

…

TargetLowering.cpp

[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364)

2023-11-10 21:38:47 +08:00