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llvm-project/llvm/lib/Target/AArch64
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Aditya Nandakumar f75d4f329c [GISel]: Provide standard interface to observe changes in GISel passes 
https://reviews.llvm.org/D54980

This provides a standard API across GISel passes to observe and notify
passes about changes (insertions/deletions/mutations) to MachineInstrs.
This patch also removes the recordInsertion method in MachineIRBuilder
and instead provides method to setObserver.

Reviewed by: vkeles.

llvm-svn: 348406
2018-12-05 20:14:52 +00:00
..
AsmParser
Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend features
2018-12-04 10:55:48 +00:00
Disassembler
[AArch64][v8.5A] Add Memory Tagging instructions
2018-10-02 10:04:39 +00:00
InstPrinter
[AArch64][v8.5A] Add Branch Target Identification instructions
2018-09-27 14:54:33 +00:00
MCTargetDesc
[TableGen] Refactor macro names (NFC)
2018-11-27 20:58:27 +00:00
TargetInfo
…
Utils
[AArch64][v8.5A] Add Branch Target Identification instructions
2018-09-27 14:54:33 +00:00
AArch64.h
AArch64: add a pass to compress jump-table entries when possible.
2018-10-24 20:19:09 +00:00
AArch64.td
[AArch64] Reword description of feature (NFC)
2018-12-05 18:42:57 +00:00
AArch64A53Fix835769.cpp
…
AArch64A57FPLoadBalancing.cpp
llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp
…
AArch64AsmPrinter.cpp
[CodeGen] Support custom format of stack maps
2018-11-26 18:43:48 +00:00
AArch64BranchTargets.cpp
[AArch64][v8.5A] Branch Target Identification code-generation pass
2018-10-08 14:04:24 +00:00
AArch64CallingConvention.h
…
AArch64CallingConvention.td
AArch64: clean up some whitespace in Windows CC (NFC)
2018-12-04 22:19:29 +00:00
AArch64CallLowering.cpp
[AArch64] Support adding X[8-15,18] registers as CSRs.
2018-09-22 22:17:50 +00:00
AArch64CallLowering.h
[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
2018-08-02 08:33:31 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
…
AArch64CompressJumpTables.cpp
AArch64: add a pass to compress jump-table entries when possible.
2018-10-24 20:19:09 +00:00
AArch64CondBrTuning.cpp
…
AArch64ConditionalCompares.cpp
…
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandPseudoInsts.cpp
[AArch64] Add Tiny Code Model for AArch64
2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp
…
AArch64FastISel.cpp
[COFF, ARM64] Implement Intrinsic.sponentry for AArch64
2018-11-01 23:22:25 +00:00
AArch64FrameLowering.cpp
[ARM64][Windows] Fix local stack size for funclets
2018-12-04 00:54:52 +00:00
AArch64FrameLowering.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
…
AArch64InstrFormats.td
Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend features
2018-12-04 10:55:48 +00:00
AArch64InstrInfo.cpp
Fix -Wparentheses warning. NFCI.
2018-12-04 12:24:10 +00:00
AArch64InstrInfo.h
[CodeGen][NFC] Make TII::getMemOpBaseImmOfs return a base operand
2018-11-28 12:00:20 +00:00
AArch64InstrInfo.td
Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend features
2018-12-04 10:55:48 +00:00
AArch64InstructionSelector.cpp
[AArch64][GlobalISel] Re-enable selection of volatile loads.
2018-12-05 00:03:09 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64][v8.5A] Add speculation restriction system registers
2018-09-27 14:05:46 +00:00
AArch64ISelLowering.cpp
[SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps
2018-11-29 19:36:17 +00:00
AArch64ISelLowering.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64LegalizerInfo.cpp
[GISel]: Provide standard interface to observe changes in GISel passes
2018-12-05 20:14:52 +00:00
AArch64LegalizerInfo.h
[GISel]: Provide standard interface to observe changes in GISel passes
2018-12-05 20:14:52 +00:00
AArch64LoadStoreOptimizer.cpp
[MI] Change the array of MachineMemOperand pointers to be
2018-08-16 21:30:05 +00:00
AArch64MachineFunctionInfo.h
[COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg
2018-10-30 20:46:10 +00:00
AArch64MacroFusion.cpp
[PATCH] [NFC][AArch64] Fix refactoring of macro fusion
2018-10-16 17:41:45 +00:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
2018-11-09 13:15:32 +00:00
AArch64PreLegalizerCombiner.cpp
[GISel]: Provide standard interface to observe changes in GISel passes
2018-12-05 20:14:52 +00:00
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBankInfo.cpp
…
AArch64RegisterBankInfo.h
…
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.h
[ARM64] [Windows] Handle funclets
2018-11-09 23:33:30 +00:00
AArch64RegisterInfo.td
[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
2018-10-08 14:09:15 +00:00
AArch64SchedA53.td
…
AArch64SchedA57.td
…
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td
…
AArch64SchedExynosM1.td
[AArch64] Refactor Exynos machine model
2018-10-24 21:40:43 +00:00
AArch64SchedExynosM3.td
[AArch64] Refactor Exynos machine model
2018-10-24 21:40:43 +00:00
AArch64SchedFalkor.td
…
AArch64SchedFalkorDetails.td
…
AArch64SchedKryo.td
…
AArch64SchedKryoDetails.td
…
AArch64SchedPredicates.td
[AArch64] Refactor the scheduling predicates (3/3) (NFC)
2018-11-26 21:47:46 +00:00
AArch64SchedThunderX2T99.td
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
2018-06-13 09:41:49 +00:00
AArch64SchedThunderX.td
…
AArch64Schedule.td
[AArch64] Refactor the scheduling predicates (3/3) (NFC)
2018-11-26 21:47:46 +00:00
AArch64SelectionDAGInfo.cpp
…
AArch64SelectionDAGInfo.h
…
AArch64SIMDInstrOpt.cpp
…
AArch64StorePairSuppress.cpp
[CodeGen][NFC] Make TII::getMemOpBaseImmOfs return a base operand
2018-11-28 12:00:20 +00:00
AArch64Subtarget.cpp
[AArch64] Refactor the scheduling predicates (1/3) (NFC)
2018-11-26 21:47:28 +00:00
AArch64Subtarget.h
AArch64: support funclets in fastcall and swift_call
2018-12-05 07:09:20 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Asm: Enable instructions to be prefixed.
2018-07-30 16:05:45 +00:00
AArch64SystemOperands.td
Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend features
2018-12-04 10:55:48 +00:00
AArch64TargetMachine.cpp
[GlobalISel] Make EnableGlobalISel always set when GISel is enabled
2018-11-29 12:56:32 +00:00
AArch64TargetMachine.h
…
AArch64TargetObjectFile.cpp
[AArch64] DWARF: do not generate AT_location for thread local
2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp
[LV] Support vectorization of interleave-groups that require an epilog under
2018-10-31 09:57:56 +00:00
AArch64TargetTransformInfo.h
[LV] Support vectorization of interleave-groups that require an epilog under
2018-10-31 09:57:56 +00:00
CMakeLists.txt
[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.
2018-11-09 13:15:32 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td
Remove extra whitespace. NFC. (test commit)
2018-09-28 08:45:28 +00:00