9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
93 lines
3.7 KiB
LLVM
93 lines
3.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}combine_ftrunc_frint_f64:
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; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]],
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; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_frint_f64(ptr addrspace(1) %p) {
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%v = load double, ptr addrspace(1) %p, align 8
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%round = tail call double @llvm.rint.f64(double %v)
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%trunc = tail call double @llvm.trunc.f64(double %round)
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store double %trunc, ptr addrspace(1) %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_frint_f32:
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; GCN: v_rndne_f32_e32 [[RND:v[0-9]+]],
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_frint_f32(ptr addrspace(1) %p) {
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%v = load float, ptr addrspace(1) %p, align 4
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%round = tail call float @llvm.rint.f32(float %v)
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%trunc = tail call float @llvm.trunc.f32(float %round)
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store float %trunc, ptr addrspace(1) %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_frint_v2f32:
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2 s[[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]]
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; GCN-DAG: v_rndne_f32_e32 v[[RND1:[0-9]+]], s[[SRC1]]
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; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]]
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; GCN: flat_store_dwordx2 v[{{[0-9:]+}}], v[[[RND1]]:[[RND2]]]
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define amdgpu_kernel void @combine_ftrunc_frint_v2f32(ptr addrspace(1) %p) {
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%v = load <2 x float>, ptr addrspace(1) %p, align 8
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%round = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %v)
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%trunc = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %round)
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store <2 x float> %trunc, ptr addrspace(1) %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_fceil_f32:
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; GCN: v_ceil_f32_e32 [[RND:v[0-9]+]],
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_fceil_f32(ptr addrspace(1) %p) {
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%v = load float, ptr addrspace(1) %p, align 4
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%round = tail call float @llvm.ceil.f32(float %v)
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%trunc = tail call float @llvm.trunc.f32(float %round)
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store float %trunc, ptr addrspace(1) %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_ffloor_f32:
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; GCN: v_floor_f32_e32 [[RND:v[0-9]+]],
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_ffloor_f32(ptr addrspace(1) %p) {
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%v = load float, ptr addrspace(1) %p, align 4
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%round = tail call float @llvm.floor.f32(float %v)
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%trunc = tail call float @llvm.trunc.f32(float %round)
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store float %trunc, ptr addrspace(1) %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_fnearbyint_f32:
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; GCN: v_rndne_f32_e32 [[RND:v[0-9]+]],
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_fnearbyint_f32(ptr addrspace(1) %p) {
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%v = load float, ptr addrspace(1) %p, align 4
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%round = tail call float @llvm.nearbyint.f32(float %v)
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%trunc = tail call float @llvm.trunc.f32(float %round)
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store float %trunc, ptr addrspace(1) %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}combine_ftrunc_ftrunc_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]],
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; GCN: v_trunc_f32_e32 [[RND:v[0-9]+]], [[SRC]]
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[RND]]
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define amdgpu_kernel void @combine_ftrunc_ftrunc_f32(ptr addrspace(1) %p) {
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%v = load float, ptr addrspace(1) %p, align 4
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%round = tail call float @llvm.trunc.f32(float %v)
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%trunc = tail call float @llvm.trunc.f32(float %round)
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store float %trunc, ptr addrspace(1) %p, align 4
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ret void
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}
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declare double @llvm.trunc.f64(double)
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declare float @llvm.trunc.f32(float)
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declare <2 x float> @llvm.trunc.v2f32(<2 x float>)
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declare double @llvm.rint.f64(double)
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declare float @llvm.rint.f32(float)
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declare <2 x float> @llvm.rint.v2f32(<2 x float>)
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declare float @llvm.ceil.f32(float)
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declare float @llvm.floor.f32(float)
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declare float @llvm.nearbyint.f32(float)
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