6206f5444f
Occupancy (i.e., the number of waves per EU) depends, in addition to register usage, on per-workgroup LDS usage as well as on the range of possible workgroup sizes. Mirroring the latter, occupancy should therefore be expressed as a range since different group sizes generally yield different achievable occupancies. `getOccupancyWithLocalMemSize` currently returns a scalar occupancy based on the maximum workgroup size and LDS usage. With respect to the workgroup size range, this scalar can be the minimum, the maximum, or neither of the two of the range of achievable occupancies. This commit fixes the function by making it compute and return the range of achievable occupancies w.r.t. workgroup size and LDS usage; it also renames it to `getOccupancyWithWorkGroupSizes` since it is the range of workgroup sizes that produces the range of achievable occupancies. Computing the achievable occupancy range is surprisingly involved. Minimum/maximum workgroup sizes do not necessarily yield maximum/minimum occupancies i.e., sometimes workgroup sizes inside the range yield the occupancy bounds. The implementation finds these sizes in constant time; heavy documentation explains the rationale behind the sometimes relatively obscure calculations. As a justifying example, consider a target with 10 waves / EU, 4 EUs/CU, 64-wide waves. Also consider a function with no LDS usage and a flat workgroup size range of [513,1024]. - A group of 513 items requires 9 waves per group. Only 4 groups made up of 9 waves each can fit fully on a CU at any given time, for a total of 36 waves on the CU, or 9 per EU. However, filling as much as possible the remaining 40-36=4 wave slots without decreasing the number of groups reveals that a larger group of 640 items yields 40 waves on the CU, or 10 per EU. - Similarly, a group of 1024 items requires 16 waves per group. Only 2 groups made up of 16 waves each can fit fully on a CU ay any given time, for a total of 32 waves on the CU, or 8 per EU. However, removing as many waves as possible from the groups without being able to fit another equal-sized group on the CU reveals that a smaller group of 896 items yields 28 waves on the CU, or 7 per EU. Therefore the achievable occupancy range for this function is not [8,9] as the group size bounds directly yield, but [7,10]. Naturally this change causes a lot of test churn as instruction scheduling is driven by achievable occupancy estimates. In most unit tests the flat workgroup size range is the default [1,1024] which, ignoring potential LDS limitations, would previously produce a scalar occupancy of 8 (derived from 1024) on a lot of targets, whereas we now consider the maximum occupancy to be 10 in such cases. Most tests are updated automatically and checked manually for sanity. I also manually changed some non-automatically generated assertions when necessary. Fixes #118220.
46 lines
1.7 KiB
LLVM
46 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Interleave loads and stores to fit into 9 VGPR limit.
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; This requires to avoid load/store clustering.
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; Reschedule the second scheduling region without clustering while
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; the first region is skipped.
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: NumVgprs: {{[0-9]$}}
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @load_store_max_9vgprs(ptr addrspace(1) nocapture noalias readonly %arg, ptr addrspace(1) nocapture noalias %arg1, i1 %cnd) #1 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%base = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i32 %id
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br i1 %cnd, label %bb1, label %bb2
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bb1:
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%tmp = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 1
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%tmp2 = load <4 x i32>, ptr addrspace(1) %tmp, align 4
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%tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 3
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%tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 4
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%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 5
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%tmp6 = load <4 x i32>, ptr addrspace(1) %tmp5, align 4
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store <4 x i32> %tmp2, ptr addrspace(1) %arg1, align 4
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%tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 3
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store <4 x i32> %tmp4, ptr addrspace(1) %tmp7, align 4
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%tmp8 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 5
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store <4 x i32> %tmp6, ptr addrspace(1) %tmp8, align 4
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br label %bb2
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bb2:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { "amdgpu-num-vgpr"="9" "amdgpu-flat-work-group-size"="1024,1024" }
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