34c8b835b1
This forced the caller to be aware of this, which is an ugly ABI feature. Partially reverts r295877. The original reasons for doing this are mostly fixed. Alloca is now in a non-0 address space, so it should be OK to have 0 as a valid pointer. Since we treat the absolute address as the pointer value, this part only really needed to apply to kernels. Since r357093, we avoid the need to increment/decrement the offset register in more cases, and since r354816 the scavenger can fail without spilling, so it's less critical that we try to avoid an offset that fits in the MUBUF offset. Restrict to callable functions for now to split this into 2 steps to limit thte number of test updates and in case anything breaks. llvm-svn: 362665
279 lines
11 KiB
LLVM
279 lines
11 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,MESA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI,MESA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,MESA %s
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target datalayout = "A5"
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; FIXME: Why is this commuted only sometimes?
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
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%add0 = add i32 %arg0, %arg1
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ret i32 %add0
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 9
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN: buffer_store_dword [[K]], off, s[0:3], s32 offset:20
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; GCN: s_waitcnt vmcnt(0)
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 68
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define fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %arg0, i32 %arg1) #1 {
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%add0 = add i32 %arg0, %arg1
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ret i32 %add0
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32:
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define hidden fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_stack_object:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 68
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_callee_stack_object:
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; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
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; GCN: s_setpc_b64
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; GCN: ; ScratchSize: 136
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_callee_stack_object(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_unused_result:
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define fastcc void @sibling_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret void
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}
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; It doesn't make sense to do a tail from a kernel
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; GCN-LABEL: {{^}}kernel_call_i32_fastcc_i32_i32_unused_result:
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;define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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ret void
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_byval_i32:
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; GCN: s_waitcnt
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; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32{{$}}
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval align 4 %arg1) #1 {
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%arg1.load = load i32, i32 addrspace(5)* %arg1, align 4
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%add0 = add i32 %arg0, %arg1.load
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ret i32 %add0
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}
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; Tail call disallowed with byval in parent.
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32_byval_parent:
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; GCN-NOT: v_writelane_b32 v{{[0-9]+}}, s32
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32{{$}}
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; GCN: s_swappc_b64
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; GCN-NOT: v_readlane_b32 s32
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval %b.byval, i32 %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* %b.byval)
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ret i32 %ret
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}
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; Tail call disallowed with byval in parent, not callee. The stack
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; usage of incoming arguments must be <= the outgoing stack
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; arguments.
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32:
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; GCN-NOT: v0
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; GCN-NOT: s32
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; GCN: buffer_load_dword v1, off, s[0:3], s4 offset:16
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; GCN: buffer_store_dword v1, off, s[0:3], s32{{$}}
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* inttoptr (i32 16 to i32 addrspace(5)*))
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}i32_fastcc_i32_i32_a32i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:4
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; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
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; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_0]]
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; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_1]]
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GFX9: v_add3_u32 v0, v0, v3, v2
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; GCN-NEXT: s_setpc_b64
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define fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %arg0, i32 %arg1, [32 x i32] %large) #1 {
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%val_firststack = extractvalue [32 x i32] %large, 30
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%val_laststack = extractvalue [32 x i32] %large, 31
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%add0 = add i32 %arg0, %arg1
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%add1 = add i32 %add0, %val_firststack
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%add2 = add i32 %add1, %val_laststack
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ret i32 %add2
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}
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; FIXME: Why load and store same location for stack args?
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32:
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; GCN-DAG: buffer_store_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
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; GCN-DAG: buffer_store_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
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; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:4
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; GCN-NOT: s32
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; GCN-DAG: buffer_store_dword [[LOAD_0]], off, s[0:3], s32{{$}}
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; GCN-DAG: buffer_store_dword [[LOAD_1]], off, s[0:3], s32 offset:4
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; GCN-DAG: buffer_load_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
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; GCN-DAG: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
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; GCN-NOT: s32
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32_stack_object:
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; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:40
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; GCN: s_setpc_b64
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32_stack_object(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; If the callee requires more stack argument space than the caller,
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; don't do a tail call.
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; TODO: Do we really need this restriction?
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; GCN-LABEL: {{^}}no_sibling_call_callee_more_stack_space:
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; GCN: s_swappc_b64
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; GCN: s_setpc_b64
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define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
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entry:
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
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ret i32 %ret
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}
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; Have another non-tail in the function
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; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_other_call:
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; GCN: s_mov_b32 s5, s32
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; GCN: s_add_u32 s32, s32, 0x400
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; GCN: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
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; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s5 offset:8
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; GCN-NEXT: s_mov_b64 exec
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; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
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; GCN: buffer_store_dword v33, off, s[0:3], s5 ; 4-byte Folded Spill
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; GCN-DAG: v_writelane_b32 v34, s33, 0
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; GCN-DAG: v_writelane_b32 v34, s34, 1
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; GCN-DAG: s_getpc_b64
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; GCN: s_swappc_b64
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; GCN: s_getpc_b64 s[6:7]
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; GCN: s_add_u32 s6, s6, sibling_call_i32_fastcc_i32_i32@rel32@lo+4
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; GCN: s_addc_u32 s7, s7, sibling_call_i32_fastcc_i32_i32@rel32@hi+4
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; GCN-DAG: v_readlane_b32 s33, v34, 0
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; GCN-DAG: v_readlane_b32 s34, v34, 1
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; GCN: buffer_load_dword v33, off, s[0:3], s5 ; 4-byte Folded Reload
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; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
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; GCN: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
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; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s5 offset:8
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; GCN-NEXT: s_mov_b64 exec
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; GCN: s_sub_u32 s32, s32, 0x400
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; GCN: s_setpc_b64 s[6:7]
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define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i32 %c) #1 {
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entry:
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%other.call = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
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%ret = tail call fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %other.call)
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ret i32 %ret
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}
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; Have stack object in caller and stack passed arguments. SP should be
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; in same place at function exit.
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; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32:
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; GCN-NOT: s33
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
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; GCN-NOT: s33
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; GCN: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
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; GCN: s_setpc_b64 s[6:7]
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define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
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ret i32 %ret
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}
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; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area:
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; GCN-NOT: s33
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:44
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; GCN-NOT: s33
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; GCN: s_setpc_b64 s[6:7]
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define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area(i32 %a, i32 %b, [36 x i32] %c) #1 {
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entry:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
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store volatile i32 9, i32 addrspace(5)* %gep
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%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
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ret i32 %ret
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline }
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