378fe2fc23
This change is part 2 x86 Loop Vectorization of :
https://github.com/llvm/llvm-project/pull/96222
It also has veclib call loop vectorization hence the test cases in
`llvm/test/Transforms/LoopVectorize/X86/veclib-calls.ll`
finally the last pr missed tests for
`llvm/test/CodeGen/X86/fp-strict-libcalls-msvc32.ll` and
`llvm/test/CodeGen/X86/vec-libcalls.ll` so added those aswell.
No evidence was found for arc and hyperbolic trig glibc vector math
functions
https://github.com/lattera/glibc/blob/master/sysdeps/x86/fpu/bits/math-vector.h
so no new `_ZGVbN2v_*` and `_ZGVdN4v_*` .
So no new tests in
`llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll`
Also no new svml and no new tests to:
`llvm/test/Transforms/LoopVectorize/X86/svml-calls.ll`
There was not enough evidence that there were svml arc and hyperbolic
trig vector implementations, Documentation was scarces so looked at test
cases in
[numpy](32bf2a9842/linux/avx512/svml_z0_acos_d_la.s (L8)).
Someone with more experience with svml should investigate.
## Note
amd libm doesn't have a vector hyperbolic sine api hence why youi might
notice there are no tests for `sinh`.
## History
This change is part of
https://github.com/llvm/llvm-project/issues/87367's investigation on
supporting IEEE math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
This change adds loop vectorization for `acos`, `asin`, `atan`, `cosh`,
`sinh`, and `tanh`.
resolves #70079
resolves #70080
resolves #70081
resolves #70083
resolves #70084
resolves #95966
1367 lines
42 KiB
LLVM
1367 lines
42 KiB
LLVM
; RUN: opt -vector-library=AMDLIBM -passes=inject-tli-mappings,loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -mattr=avx -S < %s | FileCheck %s
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|
; RUN: opt -vector-library=AMDLIBM -passes=inject-tli-mappings,loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -mattr=avx -S < %s | FileCheck %s --check-prefix=CHECK-AVX-VF2
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|
; RUN: opt -vector-library=AMDLIBM -passes=inject-tli-mappings,loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -mattr=+avx512f -S < %s | FileCheck %s --check-prefix=CHECK-AVX512-VF8
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; RUN: opt -vector-library=AMDLIBM -passes=inject-tli-mappings,loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -mattr=+avx512f -S < %s | FileCheck %s --check-prefix=CHECK-AVX512-VF16
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|
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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|
declare double @sin(double) #0
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declare float @sinf(float) #0
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declare double @llvm.sin.f64(double) #0
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declare float @llvm.sin.f32(float) #0
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|
declare double @cos(double) #0
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declare float @cosf(float) #0
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declare double @llvm.cos.f64(double) #0
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declare float @llvm.cos.f32(float) #0
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declare double @tan(double) #0
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declare float @tanf(float) #0
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declare double @llvm.tan.f64(double) #0
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declare float @llvm.tan.f32(float) #0
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declare float @acosf(float) #0
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declare float @llvm.acos.f32(float) #0
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declare double @asin(double) #0
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declare float @asinf(float) #0
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declare double @llvm.asin.f64(double) #0
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declare float @llvm.asin.f32(float) #0
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declare double @atan(double) #0
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declare float @atanf(float) #0
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declare double @llvm.atan.f64(double) #0
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declare float @llvm.atan.f32(float) #0
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declare double @cosh(double) #0
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declare float @coshf(float) #0
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declare double @llvm.cosh.f64(double) #0
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declare float @llvm.cosh.f32(float) #0
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declare float @tanhf(float) #0
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declare float @llvm.tanh.f32(float) #0
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declare double @pow(double, double) #0
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declare float @powf(float, float) #0
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declare double @llvm.pow.f64(double, double) #0
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declare float @llvm.pow.f32(float, float) #0
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declare double @exp(double) #0
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declare float @expf(float) #0
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declare double @llvm.exp.f64(double) #0
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declare float @llvm.exp.f32(float) #0
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declare double @log(double) #0
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declare float @logf(float) #0
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declare double @llvm.log.f64(double) #0
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declare float @llvm.log.f32(float) #0
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declare double @log2(double) #0
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declare float @log2f(float) #0
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declare double @llvm.log2.f64(double) #0
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declare float @llvm.log2.f32(float) #0
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declare double @log10(double) #0
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declare float @log10f(float) #0
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declare double @llvm.log10.f64(double) #0
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declare float @llvm.log10.f32(float) #0
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declare double @sqrt(double) #0
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declare float @sqrtf(float) #0
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declare double @exp2(double) #0
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declare float @exp2f(float) #0
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declare double @llvm.exp2.f64(double) #0
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declare float @llvm.exp2.f32(float) #0
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define void @sin_f64(ptr nocapture %varray) {
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; CHECK-LABEL: @sin_f64(
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; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_sin(<4 x double> [[TMP4:%.*]])
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; CHECK: ret void
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;
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; CHECK-AVX512-VF8-LABEL: @sin_f64(
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; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_sin(<8 x double> [[TMP4:%.*]])
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; CHECK-AVX512-VF8: ret void
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|
;
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entry:
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br label %for.body
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|
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%tmp = trunc i64 %iv to i32
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%conv = sitofp i32 %tmp to double
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%call = tail call double @sin(double %conv)
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%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
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|
store double %call, ptr %arrayidx, align 4
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|
%iv.next = add nuw nsw i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 1000
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|
br i1 %exitcond, label %for.end, label %for.body
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|
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|
for.end:
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ret void
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|
}
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define void @sin_f32(ptr nocapture %varray) {
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; CHECK-LABEL: @sin_f32(
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; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_sinf(<4 x float> [[TMP4:%.*]])
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; CHECK: ret void
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;
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; CHECK-AVX512-VF16-LABEL: @sin_f32(
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; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_sinf(<16 x float> [[TMP4:%.*]])
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; CHECK-AVX512-VF16: ret void
|
|
;
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|
entry:
|
|
br label %for.body
|
|
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|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%tmp = trunc i64 %iv to i32
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%conv = sitofp i32 %tmp to float
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|
%call = tail call float @sinf(float %conv)
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%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
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store float %call, ptr %arrayidx, align 4
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|
%iv.next = add nuw nsw i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 1000
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|
br i1 %exitcond, label %for.end, label %for.body
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|
|
for.end:
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ret void
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|
}
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define void @sin_f64_intrinsic(ptr nocapture %varray) {
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; CHECK-LABEL: @sin_f64_intrinsic(
|
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; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_sin(<4 x double> [[TMP4:%.*]])
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|
; CHECK: ret void
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|
;
|
|
; CHECK-AVX512-VF8-LABEL: @sin_f64_intrinsic(
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; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_sin(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
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|
%conv = sitofp i32 %tmp to double
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|
%call = tail call double @llvm.sin.f64(double %conv)
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|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
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|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @sin_f32_intrinsic(ptr nocapture %varray) {
|
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; CHECK-LABEL: @sin_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_sinf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @sin_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_sinf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.sin.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cos_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cos_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_cos(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @cos_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_cos(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @cos(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cos_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cos_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_cosf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @cos_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_cosf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @cosf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cos_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cos_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_cos(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @cos_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_cos(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.cos.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cos_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cos_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_cosf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @cos_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_cosf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.cos.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tan_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tan_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_tan(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX-VF2-LABEL: @tan_f64(
|
|
; CHECK-AVX-VF2: [[TMP5:%.*]] = call <2 x double> @amd_vrd2_tan(<2 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX-VF2: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @tan_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_tan(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @tan(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tan_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tan_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_tanf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @tan_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_tanf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @tanf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tan_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tan_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_tan(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX-VF2-LABEL: @tan_f64_intrinsic(
|
|
; CHECK-AVX-VF2: [[TMP5:%.*]] = call <2 x double> @amd_vrd2_tan(<2 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX-VF2: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @tan_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_tan(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.tan.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tan_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tan_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_tanf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @tan_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_tanf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.tan.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @acos_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @acos_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_acosf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @acosf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @acos_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @acos_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_acosf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.acos.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @asin_f64(ptr nocapture %varray) {
|
|
; CHECK-AVX512-VF8-LABEL: @asin_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_asin(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @asin(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @asin_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @asin_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_asinf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @asin_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_asinf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @asinf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @asin_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-AVX512-VF8-LABEL: @asin_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_asin(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.asin.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @asin_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @asin_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_asinf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @asin_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_asinf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.asin.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @atan_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @atan_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_atan(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX-VF2-LABEL: @atan_f64(
|
|
; CHECK-AVX-VF2: [[TMP5:%.*]] = call <2 x double> @amd_vrd2_atan(<2 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX-VF2: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @atan_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_atan(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @atan(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @atan_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @atan_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_atanf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @atan_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_atanf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @atanf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @atan_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @atan_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_atan(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX-VF2-LABEL: @atan_f64_intrinsic(
|
|
; CHECK-AVX-VF2: [[TMP5:%.*]] = call <2 x double> @amd_vrd2_atan(<2 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX-VF2: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @atan_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_atan(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.atan.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @atan_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @atan_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_atanf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @atan_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_atanf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.atan.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cosh_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cosh_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_coshf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @coshf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @cosh_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @cosh_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_coshf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.cosh.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tanh_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tanh_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_tanhf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @tanhf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @tanh_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @tanh_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_tanhf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.tanh.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @pow_f64(ptr nocapture %varray, ptr nocapture readonly %exp) {
|
|
; CHECK-LABEL: @pow_f64(
|
|
; CHECK: [[TMP8:%.*]] = call <4 x double> @amd_vrd4_pow(<4 x double> [[TMP4:%.*]], <4 x double> [[WIDE_LOAD:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @pow_f64(
|
|
; CHECK-AVX512-VF8: [[TMP8:%.*]] = call <8 x double> @amd_vrd8_pow(<8 x double> [[TMP4:%.*]], <8 x double> [[WIDE_LOAD:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%arrayidx = getelementptr inbounds double, ptr %exp, i64 %iv
|
|
%tmp1 = load double, ptr %arrayidx, align 4
|
|
%tmp2 = tail call double @pow(double %conv, double %tmp1)
|
|
%arrayidx2 = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %tmp2, ptr %arrayidx2, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @pow_f64_intrinsic(ptr nocapture %varray, ptr nocapture readonly %exp) {
|
|
; CHECK-LABEL: @pow_f64_intrinsic(
|
|
; CHECK: [[TMP8:%.*]] = call <4 x double> @amd_vrd4_pow(<4 x double> [[TMP4:%.*]], <4 x double> [[WIDE_LOAD:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @pow_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP8:%.*]] = call <8 x double> @amd_vrd8_pow(<8 x double> [[TMP4:%.*]], <8 x double> [[WIDE_LOAD:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%arrayidx = getelementptr inbounds double, ptr %exp, i64 %iv
|
|
%tmp1 = load double, ptr %arrayidx, align 4
|
|
%tmp2 = tail call double @llvm.pow.f64(double %conv, double %tmp1)
|
|
%arrayidx2 = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %tmp2, ptr %arrayidx2, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @pow_f32(ptr nocapture %varray, ptr nocapture readonly %exp) {
|
|
; CHECK-LABEL: @pow_f32(
|
|
; CHECK: [[TMP8:%.*]] = call <4 x float> @amd_vrs4_powf(<4 x float> [[TMP4:%.*]], <4 x float> [[WIDE_LOAD:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @pow_f32(
|
|
; CHECK-AVX512-VF16: [[TMP8:%.*]] = call <16 x float> @amd_vrs16_powf(<16 x float> [[TMP4:%.*]], <16 x float> [[WIDE_LOAD:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%arrayidx = getelementptr inbounds float, ptr %exp, i64 %iv
|
|
%tmp1 = load float, ptr %arrayidx, align 4
|
|
%tmp2 = tail call float @powf(float %conv, float %tmp1)
|
|
%arrayidx2 = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %tmp2, ptr %arrayidx2, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @pow_f32_intrinsic(ptr nocapture %varray, ptr nocapture readonly %exp) {
|
|
; CHECK-LABEL: @pow_f32_intrinsic(
|
|
; CHECK: [[TMP8:%.*]] = call <4 x float> @amd_vrs4_powf(<4 x float> [[TMP4:%.*]], <4 x float> [[WIDE_LOAD:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @pow_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP8:%.*]] = call <16 x float> @amd_vrs16_powf(<16 x float> [[TMP4:%.*]], <16 x float> [[WIDE_LOAD:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%arrayidx = getelementptr inbounds float, ptr %exp, i64 %iv
|
|
%tmp1 = load float, ptr %arrayidx, align 4
|
|
%tmp2 = tail call float @llvm.pow.f32(float %conv, float %tmp1)
|
|
%arrayidx2 = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %tmp2, ptr %arrayidx2, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_exp(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @exp_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_exp(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @exp(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_expf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @exp_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_expf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @expf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_exp(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @exp_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_exp(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.exp.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_expf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @exp_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_expf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.exp.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_log(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @log_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_log(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @log(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_logf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_logf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @logf(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_log(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @log_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_log(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.log.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_logf(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_logf(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.log.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log2_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log2_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_log2(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @log2_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_log2(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @log2(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log2_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log2_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_log2f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log2_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_log2f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @log2f(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log2_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log2_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_log2(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @log2_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_log2(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.log2.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log2_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log2_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_log2f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log2_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_log2f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.log2.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log10_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log10_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_log10f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log10_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_log10f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @log10f(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @log10_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @log10_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_log10f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @log10_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_log10f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.log10.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp2_f64(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp2_f64(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_exp2(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @exp2_f64(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_exp2(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @exp2(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp2_f32(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp2_f32(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_exp2f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @exp2_f32(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_exp2f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @exp2f(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp2_f64_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp2_f64_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x double> @amd_vrd4_exp2(<4 x double> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF8-LABEL: @exp2_f64_intrinsic(
|
|
; CHECK-AVX512-VF8: [[TMP5:%.*]] = call <8 x double> @amd_vrd8_exp2(<8 x double> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF8: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to double
|
|
%call = tail call double @llvm.exp2.f64(double %conv)
|
|
%arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
|
|
store double %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
define void @exp2_f32_intrinsic(ptr nocapture %varray) {
|
|
; CHECK-LABEL: @exp2_f32_intrinsic(
|
|
; CHECK: [[TMP5:%.*]] = call <4 x float> @amd_vrs4_exp2f(<4 x float> [[TMP4:%.*]])
|
|
; CHECK: ret void
|
|
;
|
|
; CHECK-AVX512-VF16-LABEL: @exp2_f32_intrinsic(
|
|
; CHECK-AVX512-VF16: [[TMP5:%.*]] = call <16 x float> @amd_vrs16_exp2f(<16 x float> [[TMP4:%.*]])
|
|
; CHECK-AVX512-VF16: ret void
|
|
;
|
|
entry:
|
|
br label %for.body
|
|
|
|
for.body:
|
|
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
|
|
%tmp = trunc i64 %iv to i32
|
|
%conv = sitofp i32 %tmp to float
|
|
%call = tail call float @llvm.exp2.f32(float %conv)
|
|
%arrayidx = getelementptr inbounds float, ptr %varray, i64 %iv
|
|
store float %call, ptr %arrayidx, align 4
|
|
%iv.next = add nuw nsw i64 %iv, 1
|
|
%exitcond = icmp eq i64 %iv.next, 1000
|
|
br i1 %exitcond, label %for.end, label %for.body
|
|
|
|
for.end:
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind readnone }
|