Simon Pilgrim f59742c1ea

[X86] getIntImmCostInst - recognise i64 ICMP EQ/NE special cases (#142812) ...

If the lower 32-bits of a i64 value are known to be zero, then icmp
lowering will shift+truncate down to a i32 allowing the immediate to be
embedded.

There's a lot more that could be done here to match icmp lowering, but
this PR just focuses on known regressions.

Fixes #142513
Fixes #62145

2025-06-06 10:21:40 +01:00

..

AArch64

[AArch64] Skip storing of stack arguments when lowering tail calls (#126735)

2025-06-06 11:26:24 +03:00

AMDGPU

[AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (#142911)

2025-06-05 10:00:24 -07:00

ARC

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ARM

Revert "[SDAG] Fix fmaximum legalization errors (#142170)"

2025-06-04 14:35:30 +02:00

AVR

[LangRef] Comment on validity of volatile ops on null (#139803)

2025-05-22 15:12:34 +02:00

BPF

[BPF] Allow struct pointee member btf generation with annotations (#141719)

2025-05-28 14:36:10 -07:00

CSKY

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DirectX

Revert "[DirectX] Array GEPs need two indices (#142853)" and "Adjust bit cast instruction filter for DXIL Prepare pass (#142678)" (#143043)

2025-06-05 20:41:37 -04:00

Generic

[DebugInfo][RemoveDIs] Delete experimental-iterator test-flags from tests (#140045)

2025-06-02 18:20:12 +01:00

Hexagon

[MachinePipeliner] Introduce a new class for loop-carried deps (#137663)

2025-06-05 21:30:27 +09:00

Inputs

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Lanai

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LoongArch

[LoongArch][NFC] Pre-commit for converting vector mask to vXi1 using [X]VMSKLTZ (#142977)

2025-06-06 16:26:17 +08:00

M68k

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Mips

[Mips] When emit instruction, ignore JUMP_TABLE_DEBUG_INFO (#139830)

2025-06-06 15:44:21 +08:00

MIR

[MIRParser] Report register class errors in a deterministic order (#142928)

2025-06-06 10:03:34 +01:00

MLRegAlloc

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MSP430

[LegalizeTypes][MSP430] Soften FAKE_USE operand (#142714)

2025-06-05 10:53:57 +09:00

NVPTX

Revert "[SDAG] Fix fmaximum legalization errors (#142170)"

2025-06-04 14:35:30 +02:00

PowerPC

[PowerPC] hoist xxspltiw instruction out of the loop with FMA mutation pass. (#111696)

2025-06-05 09:41:51 -04:00

RISCV

[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)

2025-06-06 11:08:23 +08:00

SPARC

[SPARC] Use op-then-halve instructions when we have VIS3

2025-05-23 22:44:05 +07:00

SPIRV

[HLSL][SPIR-V] Implement vk::ext_builtin_input attribute (#138530)

2025-06-04 13:22:37 +02:00

SystemZ

[MCP] Disable BackwardCopyPropagateBlock for copies with implicit registers. (#137687)

2025-05-08 16:27:08 -07:00

Thumb

[MC][AArch64][ARM][X86] Push target-dependent assembler flags into targets (#139844)

2025-05-18 20:09:43 +01:00

Thumb2

[ARM]: codegen llvm.roundeven.v* (#141786)

2025-05-30 19:36:29 +01:00

VE

Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)

2025-04-22 17:36:41 -04:00

WebAssembly

[WebAssembly] Fix trunc in FastISel (#138479)

2025-05-06 14:16:35 -07:00

WinCFGuard

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WinEH

[WinEH] Fix asm in catchpad being turned into unreachable (#138392)

2025-05-08 21:46:51 +02:00

X86

[X86] getIntImmCostInst - recognise i64 ICMP EQ/NE special cases (#142812)

2025-06-06 10:21:40 +01:00

XCore

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Xtensa

[Xtensa] Implement Xtensa Mul and Div Options. (#132157)

2025-04-18 20:22:03 +03:00