f09cf34d00
This is a fairly large changeset, but it can be broken into a few pieces: - `llvm/Support/*TargetParser*` are all moved from the LLVM Support component into a new LLVM Component called "TargetParser". This potentially enables using tablegen to maintain this information, as is shown in https://reviews.llvm.org/D137517. This cannot currently be done, as llvm-tblgen relies on LLVM's Support component. - This also moves two files from Support which use and depend on information in the TargetParser: - `llvm/Support/Host.{h,cpp}` which contains functions for inspecting the current Host machine for info about it, primarily to support getting the host triple, but also for `-mcpu=native` support in e.g. Clang. This is fairly tightly intertwined with the information in `X86TargetParser.h`, so keeping them in the same component makes sense. - `llvm/ADT/Triple.h` and `llvm/Support/Triple.cpp`, which contains the target triple parser and representation. This is very intertwined with the Arm target parser, because the arm architecture version appears in canonical triples on arm platforms. - I moved the relevant unittests to their own directory. And so, we end up with a single component that has all the information about the following, which to me seems like a unified component: - Triples that LLVM Knows about - Architecture names and CPUs that LLVM knows about - CPU detection logic for LLVM Given this, I have also moved `RISCVISAInfo.h` into this component, as it seems to me to be part of that same set of functionality. If you get link errors in your components after this patch, you likely need to add TargetParser into LLVM_LINK_COMPONENTS in CMake. Differential Revision: https://reviews.llvm.org/D137838
89 lines
2.1 KiB
CMake
89 lines
2.1 KiB
CMake
add_llvm_component_group(PowerPC HAS_JIT)
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set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
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tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
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tablegen(LLVM PPCGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM PPCGenGlobalISel.inc -gen-global-isel)
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add_public_tablegen_target(PowerPCCommonTableGen)
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add_llvm_target(PowerPCCodeGen
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GISel/PPCInstructionSelector.cpp
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PPCBoolRetToInt.cpp
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCBranchCoalescing.cpp
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PPCCallingConv.cpp
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PPCCCState.cpp
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PPCCTRLoops.cpp
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PPCCTRLoopsVerify.cpp
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PPCExpandAtomicPseudoInsts.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCEarlyReturn.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCLoopInstrFormPrep.cpp
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PPCMCInstLower.cpp
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PPCMachineFunctionInfo.cpp
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PPCMachineScheduler.cpp
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PPCMacroFusion.cpp
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PPCMIPeephole.cpp
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PPCRegisterInfo.cpp
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PPCSubtarget.cpp
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PPCTargetMachine.cpp
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PPCTargetObjectFile.cpp
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PPCTargetTransformInfo.cpp
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PPCTOCRegDeps.cpp
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PPCTLSDynamicCall.cpp
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PPCVSXCopy.cpp
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PPCReduceCRLogicals.cpp
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PPCVSXFMAMutate.cpp
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PPCVSXSwapRemoval.cpp
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PPCExpandISEL.cpp
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PPCPreEmitPeephole.cpp
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PPCLowerMASSVEntries.cpp
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PPCGenScalarMASSEntries.cpp
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GISel/PPCCallLowering.cpp
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GISel/PPCRegisterBankInfo.cpp
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GISel/PPCLegalizerInfo.cpp
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LINK_COMPONENTS
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Analysis
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AsmPrinter
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BinaryFormat
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CodeGen
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Core
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MC
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PowerPCDesc
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PowerPCInfo
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Scalar
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SelectionDAG
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Support
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Target
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TargetParser
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TransformUtils
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GlobalISel
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ADD_TO_COMPONENT
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PowerPC
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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