5351878ba1
Summary: The existing undefined-bitfield-to-operand matching behavior is very hard to understand, due to the combination of positional and named matching. This can make it difficult to track down a bug in a target's instruction definitions. Over the last decade, folks have tried to work-around this in various ways, but it's time to finally ditch the positional matching. With https://reviews.llvm.org/D131003, there are no longer cases that _require_ positional matching, and it's time to start removing usage and support for it. Therefore: add a (default-false) option, and set it to true only in those targets that require positional matching today. Subsequent changes will start cleaning up additional in-tree targets. NOTE TO OUT OF TREE TARGET MAINTAINERS: If this change breaks your build, you may restore the previous behavior simply by adding: let useDeprecatedPositionallyEncodedOperands = 1; to your target's InstrInfo tablegen definition. However, this is temporary -- the option will be removed in the future. If your target does not set 'decodePositionallyEncodedOperands', you may thus start migrating to named operands. However, if you _do_ currently set that option, I recommend waiting until a subsequent change lands, which adds decoder support for named sub-operands. Differential Revision: https://reviews.llvm.org/D134073
70 lines
2.4 KiB
TableGen
70 lines
2.4 KiB
TableGen
//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// VE Subtarget features.
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//
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def FeatureEnableVPU
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: SubtargetFeature<"vpu", "EnableVPU", "true",
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"Enable the VPU">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "VERegisterInfo.td"
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include "VECallingConv.td"
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include "VEInstrInfo.td"
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def VEInstrInfo : InstrInfo {
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let useDeprecatedPositionallyEncodedOperands = 1;
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}
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def VEAsmParser : AsmParser {
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// Use both VE register name matcher to accept "S0~S63" register names
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// and default register matcher to accept other registeres.
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let AllowDuplicateRegisterNames = 1;
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let ShouldEmitMatchRegisterAltName = 1;
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}
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//===----------------------------------------------------------------------===//
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// VE processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def VEAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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}
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def VE : Target {
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// Pull in Instruction Info:
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let InstructionSet = VEInstrInfo;
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let AssemblyParsers = [VEAsmParser];
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let AssemblyWriters = [VEAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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