f62d8a1a50
Before this patch: - For `r = or op0, op1`, `tryBitfieldInsertOpFromOr` combines it to BFI when 1) one of the two operands is bit-field-positioning or bit-field-extraction op; and 2) bits from the two operands don't overlap After this patch: - Right before OR is combined to BFI, evaluates if ORR with left-shifted operand is better. A motivating example (https://godbolt.org/z/rnMrzs5vn, which is added as a test case in `test_orr_not_bfi` in `CodeGen/AArch64/bitfield-insert.ll`) For IR: ``` define i64 @test_orr_not_bfxil(i64 %0) { %2 = and i64 %0, 127 %3 = lshr i64 %0, 1 %4 = and i64 %3, 16256 %5 = or i64 %4, %2 ret i64 %5 } ``` Before: ``` lsr x8, x0, #1 and x8, x8, #0x3f80 bfxil x8, x0, #0, #7 ``` After: ``` ubfx x8, x0, #8, #7 and x9, x0, #0x7f orr x0, x9, x8, lsl #7 ``` Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D135102
227 lines
6.5 KiB
LLVM
227 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; When first 2 operands match, it's a rotate.
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define i8 @rotl_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotl_i8_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ubfx w8, w0, #5, #3
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; CHECK-NEXT: orr w0, w8, w0, lsl #3
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i64 @rotl_i64_const_shift(i64 %x) {
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; CHECK-LABEL: rotl_i64_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror x0, x0, #61
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
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ret i64 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotl_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotl_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w1
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; CHECK-NEXT: and w9, w1, #0xf
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; CHECK-NEXT: and w8, w8, #0xf
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; CHECK-NEXT: and w10, w0, #0xffff
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; CHECK-NEXT: lsl w9, w0, w9
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; CHECK-NEXT: lsr w8, w10, w8
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; CHECK-NEXT: orr w0, w9, w8
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; CHECK-NEXT: ret
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%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotl_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotl_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w1
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; CHECK-NEXT: ror w0, w0, w8
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotl_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotl_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w1
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; CHECK-NEXT: ror x0, x0, x8
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; CHECK-LABEL: rotl_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.4s, #31
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; CHECK-NEXT: neg v3.4s, v1.4s
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
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; CHECK-NEXT: neg v2.4s, v2.4s
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; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
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; CHECK-LABEL: rotl_v4i32_rotl_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.4s, v0.4s, #29
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; CHECK-NEXT: shl v0.4s, v0.4s, #3
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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; Repeat everything for funnel shift right.
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; When first 2 operands match, it's a rotate.
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define i8 @rotr_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotr_i8_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #5
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; CHECK-NEXT: bfxil w8, w0, #3, #5
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: ret
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%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i32 @rotr_i32_const_shift(i32 %x) {
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; CHECK-LABEL: rotr_i32_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w0, w0, #3
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
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ret i32 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotr_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotr_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w1
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; CHECK-NEXT: and w9, w1, #0xf
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; CHECK-NEXT: and w8, w8, #0xf
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; CHECK-NEXT: and w10, w0, #0xffff
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; CHECK-NEXT: lsr w9, w10, w9
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; CHECK-NEXT: lsl w8, w0, w8
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; CHECK-NEXT: orr w0, w9, w8
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; CHECK-NEXT: ret
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotr_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotr_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w0, w0, w1
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotr_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotr_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror x0, x0, x1
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; CHECK-LABEL: rotr_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.4s, #31
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; CHECK-NEXT: neg v3.4s, v1.4s
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
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; CHECK-NEXT: ushl v2.4s, v0.4s, v2.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
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; CHECK-LABEL: rotr_v4i32_const_shift:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v1.4s, v0.4s, #29
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; CHECK-NEXT: ushr v0.4s, v0.4s, #3
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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