3a894fd90b
As suggested in D12425 it would be better for the readcyclecounter function on ARM architecture to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a PMU register which, depending on the configuration, it might always return zeroes and it doesn't guaranteed to always be increased. Differential Revision: https://reviews.llvm.org/D136999
14 lines
486 B
LLVM
14 lines
486 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;; -mattr=+all is not intended to be used for code emitters. Nevertheless,
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;; llc does not reject it. This test intends to catch behavior changes.
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; RUN: llc -mtriple=aarch64 -mattr=+all < %s | FileCheck %s
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define half @bf16() nounwind {
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; CHECK-LABEL: bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr h0, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: ret
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ret half 0xH0000
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}
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