212 lines
7.6 KiB
LLVM
212 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
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declare half @llvm.amdgcn.ldexp.f16(half %a, i32 %b)
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define amdgpu_kernel void @ldexp_f16(
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; VI-LABEL: ldexp_f16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_mov_b32 s14, s2
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s12, s6
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; VI-NEXT: s_mov_b32 s13, s7
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; VI-NEXT: s_mov_b32 s15, s3
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; VI-NEXT: s_mov_b32 s10, s2
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; VI-NEXT: s_mov_b32 s11, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
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; VI-NEXT: buffer_load_dword v1, off, s[8:11], 0
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_ldexp_f16_e32 v0, v0, v1
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; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: ldexp_f16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; GFX10-NEXT: s_mov_b32 s2, -1
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; GFX10-NEXT: s_mov_b32 s3, 0x31016000
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; GFX10-NEXT: s_mov_b32 s14, s2
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; GFX10-NEXT: s_mov_b32 s15, s3
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; GFX10-NEXT: s_mov_b32 s10, s2
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; GFX10-NEXT: s_mov_b32 s11, s3
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s12, s6
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; GFX10-NEXT: s_mov_b32 s13, s7
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; GFX10-NEXT: buffer_load_ushort v0, off, s[12:15], 0
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; GFX10-NEXT: buffer_load_dword v1, off, s[8:11], 0
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; GFX10-NEXT: s_mov_b32 s0, s4
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; GFX10-NEXT: s_mov_b32 s1, s5
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1
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; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: ldexp_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
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; GFX11-NEXT: s_mov_b32 s10, -1
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; GFX11-NEXT: s_mov_b32 s11, 0x31016000
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; GFX11-NEXT: s_mov_b32 s14, s10
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; GFX11-NEXT: s_mov_b32 s15, s11
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; GFX11-NEXT: s_mov_b32 s2, s10
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; GFX11-NEXT: s_mov_b32 s3, s11
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 s12, s6
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; GFX11-NEXT: s_mov_b32 s13, s7
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; GFX11-NEXT: buffer_load_u16 v0, off, s[12:15], 0
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; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
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; GFX11-NEXT: s_mov_b32 s8, s4
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; GFX11-NEXT: s_mov_b32 s9, s5
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_ldexp_f16_e32 v0, v0, v1
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; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b) {
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%a.val = load half, ptr addrspace(1) %a
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%b.val = load i32, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.ldexp.f16(half %a.val, i32 %b.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @ldexp_f16_imm_a(
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; VI-LABEL: ldexp_f16_imm_a:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_mov_b32 s10, s6
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; VI-NEXT: s_mov_b32 s11, s7
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s8, s2
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; VI-NEXT: s_mov_b32 s9, s3
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; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
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; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: ldexp_f16_imm_a:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: s_mov_b32 s6, -1
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; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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; GFX10-NEXT: s_mov_b32 s10, s6
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; GFX10-NEXT: s_mov_b32 s11, s7
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s8, s2
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; GFX10-NEXT: s_mov_b32 s9, s3
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; GFX10-NEXT: s_mov_b32 s4, s0
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; GFX10-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GFX10-NEXT: s_mov_b32 s5, s1
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
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; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: ldexp_f16_imm_a:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s10, s6
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; GFX11-NEXT: s_mov_b32 s11, s7
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 s8, s2
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; GFX11-NEXT: s_mov_b32 s9, s3
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; GFX11-NEXT: s_mov_b32 s4, s0
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; GFX11-NEXT: buffer_load_b32 v0, off, s[8:11], 0
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; GFX11-NEXT: s_mov_b32 s5, s1
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_ldexp_f16_e32 v0, 2.0, v0
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; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %b) {
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%b.val = load i32, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.ldexp.f16(half 2.0, i32 %b.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @ldexp_f16_imm_b(
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; VI-LABEL: ldexp_f16_imm_b:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_mov_b32 s10, s6
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; VI-NEXT: s_mov_b32 s11, s7
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s8, s2
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; VI-NEXT: s_mov_b32 s9, s3
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; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_ldexp_f16_e64 v0, v0, 2
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; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: ldexp_f16_imm_b:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: s_mov_b32 s6, -1
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; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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; GFX10-NEXT: s_mov_b32 s10, s6
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; GFX10-NEXT: s_mov_b32 s11, s7
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s8, s2
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; GFX10-NEXT: s_mov_b32 s9, s3
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; GFX10-NEXT: s_mov_b32 s4, s0
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; GFX10-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; GFX10-NEXT: s_mov_b32 s5, s1
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_ldexp_f16_e64 v0, v0, 2
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; GFX10-NEXT: buffer_store_short v0, off, s[4:7], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: ldexp_f16_imm_b:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s10, s6
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; GFX11-NEXT: s_mov_b32 s11, s7
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 s8, s2
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; GFX11-NEXT: s_mov_b32 s9, s3
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; GFX11-NEXT: s_mov_b32 s4, s0
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; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0
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; GFX11-NEXT: s_mov_b32 s5, s1
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_ldexp_f16_e64 v0, v0, 2
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; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call half @llvm.amdgcn.ldexp.f16(half %a.val, i32 2)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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