b4e1b0e00d
Each dead def of the same virtual register is required to be split into multiple virtual registers with separate live intervals to avoid MachineVerifier error. Partially fixes https://github.com/llvm/llvm-project/issues/56050 and https://github.com/llvm/llvm-project/issues/56051 Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D130477
488 lines
14 KiB
YAML
488 lines
14 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
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# GCN: name: negated_cond_vop2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop2_redef_vcc1
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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# GCN-NEXT: $vcc_lo = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_redef_vcc1
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc_lo = COPY $sgpr0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop2_redef_vcc2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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# GCN-NEXT: $vcc_hi = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_redef_vcc2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc_hi = COPY $sgpr0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_redef_cmp
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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# GCN-NEXT: %2.sub1:sreg_64_xexec = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_redef_cmp
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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%2.sub1 = COPY $sgpr0
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_undef_vcc
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# GCN: $vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_undef_vcc
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body: |
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bb.0:
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$vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_imp_vcc
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# GCN: $vcc = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_imp_vcc
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop2_imp_vcc
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# GCN: $vcc = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_imp_vcc
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $vcc, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 killed $vcc, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_redef_sel
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: dead %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_redef_sel
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%1:vgpr_32 = COPY $vgpr0
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop2_used_sel
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_used_sel
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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$vgpr0 = COPY %1
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S_ENDPGM 0, implicit $vgpr0
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...
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# GCN: name: negated_cond_vop2_used_vcc
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_used_vcc
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$sgpr0_sgpr1 = COPY $vcc
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0, implicit $vgpr0
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...
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# GCN: name: negated_cond_vop3_sel_wrong_subreg1
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_sel_wrong_subreg1
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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undef %1.sub1 = IMPLICIT_DEF
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%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_sel_wrong_subreg2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_sel_wrong_subreg2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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undef %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%1.sub1 = IMPLICIT_DEF
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_sel_right_subreg1
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_sel_right_subreg1
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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undef %1.sub1 = IMPLICIT_DEF
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%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_sel_right_subreg2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_sel_right_subreg2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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undef %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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%1.sub1 = IMPLICIT_DEF
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN: name: negated_cond_vop3_sel_subreg_overlap
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1.sub2:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
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# GCN-NEXT: %1.sub2_sub3:vreg_128 = IMPLICIT_DEF
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
|
---
|
|
name: negated_cond_vop3_sel_subreg_overlap
|
|
body: |
|
|
bb.0:
|
|
%0:sreg_64_xexec = IMPLICIT_DEF
|
|
undef %1.sub2:vreg_128 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
|
|
%1.sub2_sub3 = IMPLICIT_DEF
|
|
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
|
|
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
|
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN: name: negated_cond_vop2_dominated_blocks
|
|
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
|
# GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
|
|
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
|
|
---
|
|
name: negated_cond_vop2_dominated_blocks
|
|
body: |
|
|
bb.0:
|
|
%0:sreg_64_xexec = IMPLICIT_DEF
|
|
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
|
|
|
|
bb.1:
|
|
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
|
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
|
S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_BRANCH %bb.1
|
|
|
|
bb.3:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN: name: negated_cond_vop2_different_blocks_cmp_and
|
|
# GCN: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
|
|
# GCN: $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc
|
|
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
|
|
---
|
|
name: negated_cond_vop2_different_blocks_cmp_and
|
|
body: |
|
|
bb.0:
|
|
%0:sreg_64_xexec = IMPLICIT_DEF
|
|
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
|
|
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
|
|
|
bb.1:
|
|
$vcc = S_AND_B64 $exec, %2, implicit-def dead $scc
|
|
S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_BRANCH %bb.1
|
|
|
|
bb.3:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN: name: negated_cond_vop2_not_dominated_blocks
|
|
# GCN: V_CNDMASK_B32_e64 0, 0, 0, 1,
|
|
# GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
|
|
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc
|
|
---
|
|
name: negated_cond_vop2_not_dominated_blocks
|
|
body: |
|
|
bb.0:
|
|
$vcc = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
%0:sreg_64_xexec = IMPLICIT_DEF
|
|
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
|
|
|
|
bb.2:
|
|
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
|
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
|
S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
|
|
S_BRANCH %bb.3
|
|
|
|
bb.3:
|
|
S_BRANCH %bb.2
|
|
|
|
bb.4:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN: name: negated_cond_subreg
|
|
# GCN: %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
|
|
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def dead $scc
|
|
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
|
---
|
|
name: negated_cond_subreg
|
|
body: |
|
|
bb.0:
|
|
undef %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
|
|
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec
|
|
undef %2.sub0_sub1:sgpr_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
|
$vcc = S_AND_B64 $exec, %2.sub0_sub1:sgpr_128, implicit-def dead $scc
|
|
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|