5ecd363295
This reverts commit 122efef8ee9be57055d204d52c38700fe933c033. - Patch fixed to not reuse definitions from predecessors in EH landing pads. - Late review suggestions (by MaskRay) have been addressed. - M68k/pipeline.ll test updated. - Init captures added in processBlock() to avoid capturing structured bindings. - RISCV has this disabled for now. Original commit message: A new pass MachineLateInstrsCleanup is added to be run after PEI. This is a simple pass that removes redundant and identical instructions whenever found by scanning the MF once while keeping track of register definitions in a map. These instructions are typically immediate loads resulting from rematerialization, and address loads emitted by target in eliminateFrameInde(). This is enabled by default, but a target could easily disable it by means of 'disablePass(&MachineLateInstrsCleanupID);'. This late cleanup is naturally not "optimal" in removing instructions as it is done by looking at phys-regs, but still quite effective. It would be desirable to improve other parts of CodeGen and avoid these redundant instructions in the first place, but there are no ideas for this yet. Differential Revision: https://reviews.llvm.org/D123394 Reviewed By: RKSimon, foad, craig.topper, arsenm, asb
210 lines
10 KiB
LLVM
210 lines
10 KiB
LLVM
; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
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; REQUIRES: asserts
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; CHECK: ModulePass Manager
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; CHECK-NEXT: Pre-ISel Intrinsic Lowering
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand large div/rem
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; CHECK-NEXT: Expand large fp convert
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: Simplify the CFG
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: MVE gather/scatter lowering
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; CHECK-NEXT: MVE lane interleaving
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Canonicalize natural loops
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
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; CHECK-NEXT: Induction Variable Users
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; CHECK-NEXT: Loop Strength Reduction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Merge contiguous icmps into a memcmp
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Expand memcmp() to load/stores
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; CHECK-NEXT: Lower Garbage Collection Instructions
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; CHECK-NEXT: Shadow Stack GC Lowering
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; CHECK-NEXT: Lower constant intrinsics
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; CHECK-NEXT: Remove unreachable blocks from the CFG
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Block Frequency Analysis
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; CHECK-NEXT: Constant Hoisting
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; CHECK-NEXT: Replace intrinsics with calls to vector library
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; CHECK-NEXT: Partially inline calls to library functions
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; CHECK-NEXT: Expand vector predication intrinsics
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; CHECK-NEXT: Scalarize Masked Memory Intrinsics
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; CHECK-NEXT: Expand reduction intrinsics
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: TLS Variable Hoist
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Transform functions to use DSP intrinsics
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; CHECK-NEXT: Complex Deinterleaving Pass
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; CHECK-NEXT: Interleaved Access Pass
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; CHECK-NEXT: Type Promotion
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; CHECK-NEXT: CodeGen Prepare
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Exception handling preparation
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; CHECK-NEXT: Merge internal globals
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Hardware Loop Insertion
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Transform predicated vector loops to use MVE tail predication
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; CHECK-NEXT: A No-Op Barrier Pass
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Safe Stack instrumentation pass
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: ARM Instruction Selection
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; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Early Tail Duplication
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; CHECK-NEXT: Optimize machine instruction PHIs
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Merge disjoint stack slots
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; CHECK-NEXT: Local Stack Slot Allocation
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Early Machine Loop Invariant Code Motion
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine Cycle Info Analysis
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Live Interval Analysis
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Modulo Software Pipelining
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: MVE TailPred and VPT Optimisation Pass
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; CHECK-NEXT: ARM MLA / MLS expansion pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: ARM pre- register allocation load / store optimization pass
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; CHECK-NEXT: ARM A15 S->D optimizer
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; CHECK-NEXT: Detect Dead Lanes
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; CHECK-NEXT: Process Implicit Definitions
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; CHECK-NEXT: Remove unreachable machine basic blocks
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; CHECK-NEXT: Live Variable Analysis
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Eliminate PHI nodes for register allocation
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; CHECK-NEXT: Two-Address instruction pass
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Live Interval Analysis
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; CHECK-NEXT: Simple Register Coalescing
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; CHECK-NEXT: Rename Disconnected Subregister Components
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; CHECK-NEXT: Machine Instruction Scheduler
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Debug Variable Analysis
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; CHECK-NEXT: Live Stack Slot Analysis
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; CHECK-NEXT: Virtual Register Map
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; CHECK-NEXT: Live Register Matrix
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; CHECK-NEXT: Bundle Machine CFG Edges
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; CHECK-NEXT: Spill Code Placement Analysis
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Greedy Register Allocator
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; CHECK-NEXT: Virtual Register Rewriter
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; CHECK-NEXT: Register Allocation Pass Scoring
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; CHECK-NEXT: Stack Slot Coloring
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Machine Loop Invariant Code Motion
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; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
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; CHECK-NEXT: Fixup Statepoint Caller Saved
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; CHECK-NEXT: PostRA Machine Sink
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Shrink Wrapping analysis
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; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK-NEXT: Machine Late Instructions Cleanup Pass
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; CHECK-NEXT: Control Flow Optimizer
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Tail Duplication
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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; CHECK-NEXT: ARM load / store optimization pass
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM Execution Domain Fix
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; CHECK-NEXT: BreakFalseDeps
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; CHECK-NEXT: ARM pseudo instruction expansion pass
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; CHECK-NEXT: Thumb2 instruction size reduce pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: If Converter
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; CHECK-NEXT: Thumb IT blocks insertion pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: PostRA Machine Instruction Scheduler
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; CHECK-NEXT: Post RA top-down list latency scheduler
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; CHECK-NEXT: MVE VPT block insertion pass
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; CHECK-NEXT: ARM Indirect Thunks
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; CHECK-NEXT: ARM sls hardening pass
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; CHECK-NEXT: Analyze Machine Code For Garbage Collection
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Branch Probability Basic Block Placement
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; CHECK-NEXT: Insert fentry calls
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; CHECK-NEXT: Insert XRay ops
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: Thumb2 instruction size reduce pass
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; CHECK-NEXT: Unpack machine instruction bundles
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: ARM block placement
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; CHECK-NEXT: optimise barriers pass
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: StackMap Liveness Analysis
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; CHECK-NEXT: Live DEBUG_VALUE analysis
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; CHECK-NEXT: Machine Sanitizer Binary Metadata
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; CHECK-NEXT: Machine Outliner
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM fix for Cortex-A57 AES Erratum 1742098
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; CHECK-NEXT: ARM Branch Targets
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: ARM constant island placement and branch shortening pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM Low Overhead Loops pass
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: ARM Assembly Printer
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; CHECK-NEXT: Free MachineFunction
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