Matt Arsenault 61be261549 MIR: Fix test error message

2022-12-22 08:58:56 -05:00

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custom-pseudo-source-values.ll

AMDGPU: Remove ImagePSV and move images to addrspace 7

2022-11-30 11:32:34 +01:00

dead-flag-on-use-operand-parse-error.mir

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empty-custom-regmask.mir

MIR: Fix parse error on empty CustomRegMask

2022-06-27 08:50:35 -04:00

expected-target-index-name.mir

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extra-imm-operand.mir

[MIR] Provide location of extra instruction operand when diagnosing it.

2022-05-20 05:56:25 +01:00

extra-reg-operand.mir

[MIR] Provide location of extra instruction operand when diagnosing it.

2022-05-20 05:56:25 +01:00

intrinsics.mir

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invalid-frame-index2.mir

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invalid-frame-index-invalid-fixed-stack.mir

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invalid-frame-index-invalid-stack.mir

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invalid-frame-index-no-stack.mir

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invalid-frame-index.mir

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invalid-target-index-operand.mir

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killed-flag-on-def-parse-error.mir

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lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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machine-function-info-after-pei.ll

Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"

2022-12-21 16:17:42 +05:30

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-no-ir.mir

Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"

2022-12-21 16:17:42 +05:30

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"

2022-12-21 16:17:42 +05:30

machine-metadata-error.mir

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machine-metadata.mir

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mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

[AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.

2022-11-14 15:36:18 +00:00

mircanon-memoperands.mir

[MIRVRegNamer] Avoid opcode hash collision

2022-11-02 13:53:12 +00:00

parse-order-reserved-regs.mir

[AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.

2022-11-14 15:36:18 +00:00

stack-id-assert.mir

Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"

2022-12-21 16:17:42 +05:30

stack-id.mir

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subreg-def-is-not-ssa.mir

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syncscopes.mir

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target-flags.mir

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target-index-operands.mir

[AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.

2022-11-14 15:36:18 +00:00

target-memoperands.mir

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vgpr-for-agpr-copy-invalid-reg.mir

AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

virtreg-uses-unallocatable-class.mir

MIR: Fix test error message

2022-12-22 08:58:56 -05:00

wwm-reserved-regs-invalid-reg.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00

wwm-reserved-regs-not-a-reg.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00

wwm-reserved-regs.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00