eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
157 lines
5.2 KiB
LLVM
157 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Make sure that a negative value for the compare-and-swap is zero extended
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; from i8/i16 to i32 since it will be compared for equality.
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; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P7
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@str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
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@str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
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@str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
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define signext i32 @main() nounwind {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0: # %L.entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: li 3, -32477
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; CHECK-NEXT: std 0, 64(1)
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; CHECK-NEXT: li 4, 234
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; CHECK-NEXT: addi 6, 1, 46
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; CHECK-NEXT: sth 3, 46(1)
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; CHECK-NEXT: lis 3, 0
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; CHECK-NEXT: ori 3, 3, 33059
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; CHECK-NEXT: sync
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; CHECK-NEXT: .LBB0_1: # %L.entry
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; CHECK-NEXT: #
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; CHECK-NEXT: lharx 5, 0, 6
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; CHECK-NEXT: cmpw 5, 3
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; CHECK-NEXT: bne 0, .LBB0_3
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; CHECK-NEXT: # %bb.2: # %L.entry
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; CHECK-NEXT: #
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; CHECK-NEXT: sthcx. 4, 0, 6
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; CHECK-NEXT: bne 0, .LBB0_1
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; CHECK-NEXT: .LBB0_3: # %L.entry
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; CHECK-NEXT: cmplwi 5, 33059
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: bne 0, .LBB0_6
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; CHECK-NEXT: # %bb.4: # %L.B0000
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; CHECK-NEXT: lhz 3, 46(1)
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; CHECK-NEXT: cmplwi 3, 234
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; CHECK-NEXT: bne 0, .LBB0_7
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; CHECK-NEXT: # %bb.5: # %L.B0001
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; CHECK-NEXT: addis 3, 2, .Lstr.2@toc@ha
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; CHECK-NEXT: addi 3, 3, .Lstr.2@toc@l
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; CHECK-NEXT: bl puts
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; CHECK-NEXT: nop
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: b .LBB0_9
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; CHECK-NEXT: .LBB0_6: # %L.B0003
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; CHECK-NEXT: addis 3, 2, .Lstr@toc@ha
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; CHECK-NEXT: addi 3, 3, .Lstr@toc@l
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; CHECK-NEXT: b .LBB0_8
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; CHECK-NEXT: .LBB0_7: # %L.B0005
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; CHECK-NEXT: addis 3, 2, .Lstr.1@toc@ha
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; CHECK-NEXT: addi 3, 3, .Lstr.1@toc@l
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; CHECK-NEXT: .LBB0_8: # %L.B0003
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; CHECK-NEXT: bl puts
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; CHECK-NEXT: nop
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: .LBB0_9: # %L.B0003
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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;
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; CHECK-P7-LABEL: main:
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; CHECK-P7: # %bb.0: # %L.entry
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; CHECK-P7-NEXT: mflr 0
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; CHECK-P7-NEXT: stdu 1, -48(1)
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; CHECK-P7-NEXT: li 3, -32477
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; CHECK-P7-NEXT: lis 5, 0
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; CHECK-P7-NEXT: addi 4, 1, 46
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; CHECK-P7-NEXT: li 7, 0
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; CHECK-P7-NEXT: std 0, 64(1)
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; CHECK-P7-NEXT: sth 3, 46(1)
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; CHECK-P7-NEXT: li 6, 234
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; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27
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; CHECK-P7-NEXT: ori 5, 5, 33059
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; CHECK-P7-NEXT: ori 7, 7, 65535
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; CHECK-P7-NEXT: sync
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; CHECK-P7-NEXT: slw 6, 6, 3
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; CHECK-P7-NEXT: slw 8, 5, 3
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; CHECK-P7-NEXT: slw 5, 7, 3
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; CHECK-P7-NEXT: rldicr 4, 4, 0, 61
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; CHECK-P7-NEXT: and 6, 6, 5
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; CHECK-P7-NEXT: and 7, 8, 5
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; CHECK-P7-NEXT: .LBB0_1: # %L.entry
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; CHECK-P7-NEXT: #
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; CHECK-P7-NEXT: lwarx 9, 0, 4
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; CHECK-P7-NEXT: and 8, 9, 5
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; CHECK-P7-NEXT: cmpw 8, 7
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; CHECK-P7-NEXT: bne 0, .LBB0_3
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; CHECK-P7-NEXT: # %bb.2: # %L.entry
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; CHECK-P7-NEXT: #
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; CHECK-P7-NEXT: andc 9, 9, 5
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; CHECK-P7-NEXT: or 9, 9, 6
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; CHECK-P7-NEXT: stwcx. 9, 0, 4
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; CHECK-P7-NEXT: bne 0, .LBB0_1
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; CHECK-P7-NEXT: .LBB0_3: # %L.entry
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; CHECK-P7-NEXT: srw 3, 8, 3
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; CHECK-P7-NEXT: lwsync
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; CHECK-P7-NEXT: cmplwi 3, 33059
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; CHECK-P7-NEXT: bne 0, .LBB0_6
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; CHECK-P7-NEXT: # %bb.4: # %L.B0000
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; CHECK-P7-NEXT: lhz 3, 46(1)
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; CHECK-P7-NEXT: cmplwi 3, 234
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; CHECK-P7-NEXT: bne 0, .LBB0_7
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; CHECK-P7-NEXT: # %bb.5: # %L.B0001
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; CHECK-P7-NEXT: addis 3, 2, .Lstr.2@toc@ha
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; CHECK-P7-NEXT: addi 3, 3, .Lstr.2@toc@l
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; CHECK-P7-NEXT: bl puts
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; CHECK-P7-NEXT: nop
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; CHECK-P7-NEXT: li 3, 0
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; CHECK-P7-NEXT: b .LBB0_9
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; CHECK-P7-NEXT: .LBB0_6: # %L.B0003
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; CHECK-P7-NEXT: addis 3, 2, .Lstr@toc@ha
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; CHECK-P7-NEXT: addi 3, 3, .Lstr@toc@l
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; CHECK-P7-NEXT: b .LBB0_8
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; CHECK-P7-NEXT: .LBB0_7: # %L.B0005
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; CHECK-P7-NEXT: addis 3, 2, .Lstr.1@toc@ha
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; CHECK-P7-NEXT: addi 3, 3, .Lstr.1@toc@l
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; CHECK-P7-NEXT: .LBB0_8: # %L.B0003
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; CHECK-P7-NEXT: bl puts
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; CHECK-P7-NEXT: nop
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; CHECK-P7-NEXT: li 3, 1
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; CHECK-P7-NEXT: .LBB0_9: # %L.B0003
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; CHECK-P7-NEXT: addi 1, 1, 48
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; CHECK-P7-NEXT: ld 0, 16(1)
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; CHECK-P7-NEXT: mtlr 0
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; CHECK-P7-NEXT: blr
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L.entry:
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%value.addr = alloca i16, align 2
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store i16 -32477, ptr %value.addr, align 2
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%0 = cmpxchg ptr %value.addr, i16 -32477, i16 234 seq_cst seq_cst
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%1 = extractvalue { i16, i1 } %0, 1
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br i1 %1, label %L.B0000, label %L.B0003
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L.B0003: ; preds = %L.entry
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%puts = call i32 @puts(ptr @str)
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ret i32 1
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L.B0000: ; preds = %L.entry
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%2 = load i16, ptr %value.addr, align 2
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%3 = icmp eq i16 %2, 234
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br i1 %3, label %L.B0001, label %L.B0005
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L.B0005: ; preds = %L.B0000
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%puts1 = call i32 @puts(ptr @str.1)
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ret i32 1
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L.B0001: ; preds = %L.B0000
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%puts2 = call i32 @puts(ptr @str.2)
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ret i32 0
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}
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; Function Attrs: nounwind
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declare i32 @puts(ptr nocapture readonly) #0
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