427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
169 lines
6.5 KiB
LLVM
169 lines
6.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -filetype=obj -code-model=large -o %t.o < %s
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; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
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; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -filetype=obj -code-model=large -o %t64.o < %s
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; RUN: llvm-readobj --relocs --expand-relocs %t64.o | FileCheck --check-prefixes=RELOC64 %s
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; RUN: llvm-objdump -D -r --symbol-description %t64.o | FileCheck --check-prefix=DIS64 %s
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@a = global i32 2, align 4
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@b = global i32 10, align 4
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@c = global i32 11, align 4
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define i32 @foo() {
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entry:
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%0 = load i32, ptr @a, align 4
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%1 = load i32, ptr @b, align 4
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%add = add nsw i32 %0, %1
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%2 = load i32, ptr @c, align 4
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%add1 = add nsw i32 %add, %2
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ret i32 %add1
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}
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; RELOC: Section (index: {{[0-9]+}}) .text {
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0x2
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; RELOC-NEXT: Symbol: a ([[#INDX:]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0x6
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; RELOC-NEXT: Symbol: a ([[#INDX]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0xE
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; RELOC-NEXT: Symbol: b ([[#INDX+2]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0x12
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; RELOC-NEXT: Symbol: b ([[#INDX+2]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0x1A
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; RELOC-NEXT: Symbol: c ([[#INDX+4]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCU (0x30)
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; RELOC-NEXT: }
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; RELOC-NEXT: Relocation {
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; RELOC-NEXT: Virtual Address: 0x1E
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; RELOC-NEXT: Symbol: c ([[#INDX+4]])
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; RELOC-NEXT: IsSigned: No
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; RELOC-NEXT: FixupBitValue: 0
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; RELOC-NEXT: Length: 16
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; RELOC-NEXT: Type: R_TOCL (0x31)
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; RELOC-NEXT: }
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; DIS: Disassembly of section .text:
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; DIS-EMPTY:
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; DIS-NEXT: 00000000 (idx: {{[0-9]+}}) .foo:
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; DIS-NEXT: 0: 3c 62 00 00 addis 3, 2, 0
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; DIS-NEXT: 00000002: R_TOCU (idx: [[#INDX:]]) a[TE]
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; DIS-NEXT: 4: 80 63 00 00 lwz 3, 0(3)
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; DIS-NEXT: 00000006: R_TOCL (idx: [[#INDX]]) a[TE]
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; DIS-NEXT: 8: 80 63 00 00 lwz 3, 0(3)
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; DIS-NEXT: c: 3c 82 00 00 addis 4, 2, 0
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; DIS-NEXT: 0000000e: R_TOCU (idx: [[#INDX+2]]) b[TE]
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; DIS-NEXT: 10: 80 84 00 04 lwz 4, 4(4)
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; DIS-NEXT: 00000012: R_TOCL (idx: [[#INDX+2]]) b[TE]
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; DIS-NEXT: 14: 80 84 00 00 lwz 4, 0(4)
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; DIS-NEXT: 18: 3c a2 00 00 addis 5, 2, 0
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; DIS-NEXT: 0000001a: R_TOCU (idx: [[#INDX+4]]) c[TE]
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; DIS-NEXT: 1c: 80 a5 00 08 lwz 5, 8(5)
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; DIS-NEXT: 0000001e: R_TOCL (idx: [[#INDX+4]]) c[TE]
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; DIS-NEXT: 20: 7c 63 22 14 add 3, 3, 4
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; DIS-NEXT: 24: 80 a5 00 00 lwz 5, 0(5)
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; DIS-NEXT: 28: 7c 63 2a 14 add 3, 3, 5
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; DIS-NEXT: 2c: 4e 80 00 20 blr
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; RELOC64: Section (index: {{[0-9]+}}) .text {
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0x2
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; RELOC64-NEXT: Symbol: a ([[#INDX:]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCU (0x30)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0x6
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; RELOC64-NEXT: Symbol: b ([[#INDX+2]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCU (0x30)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0xA
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; RELOC64-NEXT: Symbol: c ([[#INDX+4]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCU (0x30)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0xE
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; RELOC64-NEXT: Symbol: a ([[#INDX]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCL (0x31)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0x12
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; RELOC64-NEXT: Symbol: b ([[#INDX+2]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCL (0x31)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: Relocation {
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; RELOC64-NEXT: Virtual Address: 0x16
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; RELOC64-NEXT: Symbol: c ([[#INDX+4]])
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; RELOC64-NEXT: IsSigned: No
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; RELOC64-NEXT: FixupBitValue: 0
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; RELOC64-NEXT: Length: 16
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; RELOC64-NEXT: Type: R_TOCL (0x31)
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; RELOC64-NEXT: }
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; RELOC64-NEXT: }
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; DIS64: Disassembly of section .text:
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; DIS64-EMPTY:
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; DIS64-NEXT: 0000000000000000 (idx: 3) .foo:
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; DIS64-NEXT: 0: 3c 62 00 00 addis 3, 2, 0
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; DIS64-NEXT: 0000000000000002: R_TOCU (idx: [[#INDX:]]) a[TE]
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; DIS64-NEXT: 4: 3c 82 00 00 addis 4, 2, 0
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; DIS64-NEXT: 0000000000000006: R_TOCU (idx: [[#INDX+2]]) b[TE]
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; DIS64-NEXT: 8: 3c a2 00 00 addis 5, 2, 0
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; DIS64-NEXT: 000000000000000a: R_TOCU (idx: [[#INDX+4]]) c[TE]
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; DIS64-NEXT: c: e8 63 00 00 ld 3, 0(3)
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; DIS64-NEXT: 000000000000000e: R_TOCL (idx: [[#INDX]]) a[TE]
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; DIS64-NEXT: 10: e8 84 00 08 ld 4, 8(4)
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; DIS64-NEXT: 0000000000000012: R_TOCL (idx: [[#INDX+2]]) b[TE]
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; DIS64-NEXT: 14: e8 a5 00 10 ld 5, 16(5)
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; DIS64-NEXT: 0000000000000016: R_TOCL (idx: [[#INDX+4]]) c[TE]
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; DIS64-NEXT: 18: 80 63 00 00 lwz 3, 0(3)
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; DIS64-NEXT: 1c: 80 84 00 00 lwz 4, 0(4)
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; DIS64-NEXT: 20: 80 a5 00 00 lwz 5, 0(5)
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; DIS64-NEXT: 24: 7c 63 22 14 add 3, 3, 4
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; DIS64-NEXT: 28: 7c 63 2a 14 add 3, 3, 5
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; DIS64-NEXT: 2c: 4e 80 00 20 blr
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