eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
80 lines
2.6 KiB
LLVM
80 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=static -verify-machineinstrs < %s --enable-shrink-wrap=false -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
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%struct.S = type { i8 }
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@sg = internal thread_local global %struct.S zeroinitializer, align 1
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@__dso_handle = external global i8
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@__tls_guard = internal thread_local unnamed_addr global i1 false
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@sum1 = internal thread_local global i32 0, align 4
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declare void @_ZN1SC1Ev(ptr)
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declare void @_ZN1SD1Ev(ptr)
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declare i32 @_tlv_atexit(ptr, ptr, ptr)
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define cxx_fast_tlscc nonnull ptr @_ZTW2sg() nounwind {
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; CHECK-LABEL: _ZTW2sg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: std 0, 64(1)
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; CHECK-NEXT: addis 3, 13, __tls_guard@tprel@ha
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; CHECK-NEXT: lbz 4, __tls_guard@tprel@l(3)
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; CHECK-NEXT: andi. 4, 4, 1
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; CHECK-NEXT: bc 12, 1, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %init.i
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: stb 4, __tls_guard@tprel@l(3)
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; CHECK-NEXT: addis 3, 13, sg@tprel@ha
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; CHECK-NEXT: addi 30, 3, sg@tprel@l
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: bl _ZN1SC1Ev
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; CHECK-NEXT: nop
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC1@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: ld 5, .LC1@toc@l(4)
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; CHECK-NEXT: mr 4, 30
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; CHECK-NEXT: bl _tlv_atexit
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_2: # %__tls_init.exit
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; CHECK-NEXT: addis 3, 13, sg@tprel@ha
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; CHECK-NEXT: addi 3, 3, sg@tprel@l
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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%.b.i = load i1, ptr @__tls_guard, align 1
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br i1 %.b.i, label %__tls_init.exit, label %init.i
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init.i:
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store i1 true, ptr @__tls_guard, align 1
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tail call void @_ZN1SC1Ev(ptr nonnull @sg) #2
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%1 = tail call i32 @_tlv_atexit(ptr nonnull @_ZN1SD1Ev, ptr nonnull @sg, ptr nonnull @__dso_handle) #2
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br label %__tls_init.exit
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__tls_init.exit:
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ret ptr @sg
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}
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define cxx_fast_tlscc nonnull ptr @_ZTW4sum1() nounwind {
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; CHECK-LABEL: _ZTW4sum1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 13, sum1@tprel@ha
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; CHECK-NEXT: addi 3, 3, sum1@tprel@l
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; CHECK-NEXT: blr
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ret ptr @sum1
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}
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define cxx_fast_tlscc ptr @_ZTW4sum2() #0 {
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; CHECK-LABEL: _ZTW4sum2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 13, sum1@tprel@ha
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; CHECK-NEXT: addi 3, 3, sum1@tprel@l
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; CHECK-NEXT: blr
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ret ptr @sum1
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}
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attributes #0 = { nounwind "frame-pointer"="all" }
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