335e8bf100
This patch changes the PowerPC backend to generate VSX load/store instructions for all vector loads/stores on Power8 and earlier (LE) instead of VMX load/store instructions. The reason for this change is because VMX instructions require the vector to be 16-byte aligned. So, a vector load/store will fail with VMX instructions if the vector is misaligned. Also, `gcc` generates VSX instructions in this situation which allow for unaligned access but require a swap instruction after loading/before storing. This is not an issue for BE because we already emit VSX instructions since no swap is required. And this is not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which allow for unaligned access and do not require swaps. This patch also delays the VSX load/store for LE combines until after LegalizeOps to prioritize other load/store combines. Reviewed By: #powerpc, stefanp Differential Revision: https://reviews.llvm.org/D127309
55 lines
2.2 KiB
LLVM
55 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
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; Check if this causes infinite loop when estimation disabled
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define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
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; CHECK-LABEL: repeated_fp_divisor_noest:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; CHECK-NEXT: lxvd2x 1, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: xxswapd 35, 1
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; CHECK-NEXT: lxvd2x 1, 0, 3
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xvdivsp 0, 35, 0
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; CHECK-NEXT: xxswapd 35, 1
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; CHECK-NEXT: xvmulsp 1, 34, 35
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; CHECK-NEXT: xvmulsp 34, 1, 0
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; CHECK-NEXT: blr
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%ins = insertelement <4 x float> undef, float %a, i32 0
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%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
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%t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
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%mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
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ret <4 x float> %mul
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}
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define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
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; CHECK-LABEL: repeated_fp_divisor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
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; CHECK-NEXT: lxvd2x 1, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l
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; CHECK-NEXT: xxswapd 1, 1
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xvresp 2, 0
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; CHECK-NEXT: xvmaddasp 1, 0, 2
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: xvnmsubasp 2, 2, 1
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; CHECK-NEXT: xvmulsp 0, 34, 35
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; CHECK-NEXT: xvmulsp 34, 0, 2
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; CHECK-NEXT: blr
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%ins = insertelement <4 x float> undef, float %a, i32 0
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%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
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%t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
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%mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat
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ret <4 x float> %mul
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}
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