7b50c18360
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included. Since most instructions are not included for Zfhmin, so most operations are promoted. The patch primarily about making f16 a legal type. RISC-V ISA info: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139391
66 lines
2.4 KiB
LLVM
66 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFHMIN %s
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define half @frem_f16(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: frem_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: fcvt.s.h fa1, fa1
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; RV32IZFH-NEXT: call fmodf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: frem_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: fcvt.s.h fa1, fa1
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; RV64IZFH-NEXT: call fmodf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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;
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; RV32IZFHMIN-LABEL: frem_f16:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: addi sp, sp, -16
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; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFHMIN-NEXT: fcvt.s.h fa1, fa1
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; RV32IZFHMIN-NEXT: call fmodf@plt
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; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFHMIN-NEXT: addi sp, sp, 16
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: frem_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: addi sp, sp, -16
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; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFHMIN-NEXT: fcvt.s.h fa1, fa1
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; RV64IZFHMIN-NEXT: call fmodf@plt
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; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFHMIN-NEXT: addi sp, sp, 16
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; RV64IZFHMIN-NEXT: ret
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%1 = frem half %a, %b
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ret half %1
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}
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