7b50c18360
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included. Since most instructions are not included for Zfhmin, so most operations are promoted. The patch primarily about making f16 a legal type. RISC-V ISA info: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139391
42 lines
1.4 KiB
LLVM
42 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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define zeroext i1 @half_is_nan(half %a) nounwind {
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; CHECK-LABEL: half_is_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.h a0, fa0, fa0
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_is_nan:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: fcvt.s.h ft0, fa0
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; CHECKIZFHMIN-NEXT: feq.s a0, ft0, ft0
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; CHECKIZFHMIN-NEXT: xori a0, a0, 1
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; CHECKIZFHMIN-NEXT: ret
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%1 = fcmp uno half %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @half_not_nan(half %a) nounwind {
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; CHECK-LABEL: half_not_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.h a0, fa0, fa0
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; CHECK-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_not_nan:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: fcvt.s.h ft0, fa0
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; CHECKIZFHMIN-NEXT: feq.s a0, ft0, ft0
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; CHECKIZFHMIN-NEXT: ret
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%1 = fcmp ord half %a, 0.000000e+00
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ret i1 %1
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}
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