29a5a7c6d4
When optimizing for size, this pass searches for instructions that are prevented from being compressed by one of the following: 1. The use of a single uncompressed register. 2. A base register + offset where the offset is too large to be compressed and the base register may or may not already be compressed. In the first case, if there is a compressed register available, then the uncompressed register is copied to the compressed register and its uses replaced. This is only done if there are enough uses that code size would be improved. In the second case, if a compressed register is available, then the original base register is copied and adjusted such that: new_base_register = base_register + adjustment base_register + large_offset = new_base_register + small_offset and the uses of the base register are replaced with the new base register. Again this is only done if there are enough uses for code size to be improved. This pass was authored by Lewis Revill, with large offset optimization added by Craig Blackmore. Differential Revision: https://reviews.llvm.org/D92105
1134 lines
47 KiB
YAML
1134 lines
47 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+f,+d -simplify-mir \
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# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV32 %s
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# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d -simplify-mir \
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# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV64 %s
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--- |
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define void @store_common_value(i32* %a, i32* %b, i32* %c) #0 {
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entry:
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store i32 0, i32* %a, align 4
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store i32 0, i32* %b, align 4
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store i32 0, i32* %c, align 4
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ret void
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}
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define void @store_common_value_float(float* %a, float* %b, float* %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j) #0 {
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entry:
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store float %j, float* %a, align 4
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store float %j, float* %b, align 4
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store float %j, float* %c, align 4
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ret void
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}
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define void @store_common_value_double(double* %a, double* %b, double* %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j) #0 {
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entry:
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store double %j, double* %a, align 8
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store double %j, double* %b, align 8
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store double %j, double* %c, align 8
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ret void
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}
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define void @store_common_ptr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32* %p) #0 {
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entry:
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store volatile i32 1, i32* %p, align 4
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store volatile i32 3, i32* %p, align 4
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store volatile i32 5, i32* %p, align 4
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ret void
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}
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define void @store_common_ptr_self(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32* %p) #0 {
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entry:
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%q = bitcast i32* %p to i32**
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store volatile i32 1, i32* %p, align 4
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store volatile i32 3, i32* %p, align 4
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store volatile i32* %p, i32** %q, align 4
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ret void
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}
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define void @store_common_ptr_float(float %a, float %b, float %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, float* %p) #0 {
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entry:
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store volatile float %a, float* %p, align 4
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store volatile float %b, float* %p, align 4
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store volatile float %c, float* %p, align 4
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ret void
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}
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define void @store_common_ptr_double(double %a, double %b, double %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, double* %p) #0 {
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entry:
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store volatile double %a, double* %p, align 8
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store volatile double %b, double* %p, align 8
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store volatile double %c, double* %p, align 8
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ret void
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}
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define void @load_common_ptr(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32* %p) #0 {
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entry:
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%g = load volatile i32, i32* %p, align 4
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%h = load volatile i32, i32* %p, align 4
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%i = load volatile i32, i32* %p, align 4
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ret void
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}
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define void @load_common_ptr_float(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, float* %g) #0 {
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entry:
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%0 = load float, float* %g, align 4
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%arrayidx1 = getelementptr inbounds float, float* %g, i32 1
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%1 = load float, float* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, float* %g, i32 2
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%2 = load float, float* %arrayidx2, align 4
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tail call void @load_common_ptr_float_1(float %0, float %1, float %2)
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ret void
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}
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declare void @load_common_ptr_float_1(float, float, float) #0
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define void @load_common_ptr_double(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, double* %g) #0 {
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entry:
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%0 = load double, double* %g, align 8
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%arrayidx1 = getelementptr inbounds double, double* %g, i32 1
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %g, i32 2
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%2 = load double, double* %arrayidx2, align 8
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tail call void @load_common_ptr_double_1(double %0, double %1, double %2)
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ret void
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}
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declare void @load_common_ptr_double_1(double, double, double) #0
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define void @store_large_offset(i32* %p) #0 {
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entry:
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%0 = getelementptr inbounds i32, i32* %p, i32 100
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store volatile i32 1, i32* %0, align 4
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%1 = getelementptr inbounds i32, i32* %p, i32 101
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store volatile i32 3, i32* %1, align 4
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%2 = getelementptr inbounds i32, i32* %p, i32 102
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store volatile i32 5, i32* %2, align 4
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%3 = getelementptr inbounds i32, i32* %p, i32 103
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store volatile i32 7, i32* %3, align 4
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ret void
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}
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define void @store_large_offset_float(float* %p, float %a, float %b, float %c, float %d) #0 {
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entry:
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%0 = getelementptr inbounds float, float* %p, i32 100
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store volatile float %a, float* %0, align 4
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%1 = getelementptr inbounds float, float* %p, i32 101
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store volatile float %b, float* %1, align 4
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%2 = getelementptr inbounds float, float* %p, i32 102
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store volatile float %c, float* %2, align 4
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%3 = getelementptr inbounds float, float* %p, i32 103
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store volatile float %d, float* %3, align 4
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ret void
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}
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define void @store_large_offset_double(double* %p, double %a, double %b, double %c, double %d) #0 {
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entry:
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%0 = getelementptr inbounds double, double* %p, i32 100
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store volatile double %a, double* %0, align 8
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%1 = getelementptr inbounds double, double* %p, i32 101
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store volatile double %b, double* %1, align 8
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%2 = getelementptr inbounds double, double* %p, i32 102
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store volatile double %c, double* %2, align 8
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%3 = getelementptr inbounds double, double* %p, i32 103
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store volatile double %d, double* %3, align 8
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ret void
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}
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define void @load_large_offset(i32* %p) #0 {
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entry:
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%0 = getelementptr inbounds i32, i32* %p, i32 100
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%a = load volatile i32, i32* %0, align 4
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%1 = getelementptr inbounds i32, i32* %p, i32 101
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%b = load volatile i32, i32* %1, align 4
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%2 = getelementptr inbounds i32, i32* %p, i32 102
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%c = load volatile i32, i32* %2, align 4
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%3 = getelementptr inbounds i32, i32* %p, i32 103
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%d = load volatile i32, i32* %3, align 4
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ret void
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}
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define void @load_large_offset_float(float* %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds float, float* %p, i32 100
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%0 = load float, float* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds float, float* %p, i32 101
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%1 = load float, float* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, float* %p, i32 102
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%2 = load float, float* %arrayidx2, align 4
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tail call void @load_large_offset_float_1(float %0, float %1, float %2)
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ret void
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}
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declare void @load_large_offset_float_1(float, float, float) #0
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define void @load_large_offset_double(double* %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds double, double* %p, i32 100
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%0 = load double, double* %arrayidx, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i32 101
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%1 = load double, double* %arrayidx1, align 8
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%arrayidx2 = getelementptr inbounds double, double* %p, i32 102
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%2 = load double, double* %arrayidx2, align 8
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tail call void @load_large_offset_double_1(double %0, double %1, double %2)
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ret void
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}
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declare void @load_large_offset_double_1(double, double, double) #0
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define void @store_common_value_no_opt(i32* %a) #0 {
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entry:
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store i32 0, i32* %a, align 4
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ret void
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}
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define void @store_common_value_float_no_opt(float* %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h) #0 {
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entry:
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store float %h, float* %a, align 4
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ret void
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}
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define void @store_common_value_double_no_opt(double* %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h) #0 {
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entry:
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store double %h, double* %a, align 8
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ret void
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}
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define void @store_common_ptr_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32* %p) #0 {
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entry:
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store volatile i32 1, i32* %p, align 4
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ret void
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}
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define void @store_common_ptr_float_no_opt(float %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, float* %p) #0 {
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entry:
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store volatile float %a, float* %p, align 4
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ret void
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}
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define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double* %p) #0 {
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entry:
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store volatile double %a, double* %p, align 8
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ret void
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}
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define void @load_common_ptr_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32* %p) #0 {
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entry:
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%g = load volatile i32, i32* %p, align 4
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ret void
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}
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define float @load_common_ptr_float_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, float* %g) #0 {
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entry:
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%0 = load float, float* %g, align 4
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ret float %0
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}
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define double @load_common_ptr_double_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, double* %g) #0 {
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entry:
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%0 = load double, double* %g, align 8
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ret double %0
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}
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define void @store_large_offset_no_opt(i32* %p) #0 {
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entry:
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%0 = getelementptr inbounds i32, i32* %p, i32 100
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store volatile i32 1, i32* %0, align 4
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%1 = getelementptr inbounds i32, i32* %p, i32 101
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store volatile i32 3, i32* %1, align 4
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ret void
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}
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define void @store_large_offset_float_no_opt(float* %p, float %a, float %b) #0 {
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entry:
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%0 = getelementptr inbounds float, float* %p, i32 100
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store volatile float %a, float* %0, align 4
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%1 = getelementptr inbounds float, float* %p, i32 101
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store volatile float %b, float* %1, align 4
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ret void
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}
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define void @store_large_offset_double_no_opt(double* %p, double %a, double %b) #0 {
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entry:
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%0 = getelementptr inbounds double, double* %p, i32 100
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store volatile double %a, double* %0, align 8
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%1 = getelementptr inbounds double, double* %p, i32 101
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store volatile double %b, double* %1, align 8
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ret void
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}
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define void @load_large_offset_no_opt(i32* %p) #0 {
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entry:
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%0 = getelementptr inbounds i32, i32* %p, i32 100
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%a = load volatile i32, i32* %0, align 4
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%1 = getelementptr inbounds i32, i32* %p, i32 101
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%b = load volatile i32, i32* %1, align 4
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ret void
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}
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define { float, float } @load_large_offset_float_no_opt(float* %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds float, float* %p, i32 100
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%0 = load float, float* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds float, float* %p, i32 101
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%1 = load float, float* %arrayidx1, align 4
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%2 = insertvalue { float, float } undef, float %0, 0
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%3 = insertvalue { float, float } %2, float %1, 1
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ret { float, float } %3
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}
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define { double, double } @load_large_offset_double_no_opt(double* %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds double, double* %p, i32 100
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%0 = load double, double* %arrayidx, align 8
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%arrayidx1 = getelementptr inbounds double, double* %p, i32 101
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%1 = load double, double* %arrayidx1, align 8
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%2 = insertvalue { double, double } undef, double %0, 0
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%3 = insertvalue { double, double } %2, double %1, 1
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ret { double, double } %3
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}
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attributes #0 = { minsize "target-features"="+c,+f,+d" }
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...
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---
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name: store_common_value
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12
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; RV32-LABEL: name: store_common_value
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; RV32: liveins: $x10, $x11, $x12
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; RV32-NEXT: {{ $}}
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; RV32-NEXT: $x13 = ADDI $x0, 0
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; RV32-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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; RV32-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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; RV32-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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; RV32-NEXT: PseudoRET
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; RV64-LABEL: name: store_common_value
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; RV64: liveins: $x10, $x11, $x12
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; RV64-NEXT: {{ $}}
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; RV64-NEXT: $x13 = ADDI $x0, 0
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; RV64-NEXT: SW $x13, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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; RV64-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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; RV64-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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; RV64-NEXT: PseudoRET
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SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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SW $x0, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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SW $x0, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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PseudoRET
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|
|
...
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---
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name: store_common_value_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12, $f16_f
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; RV32-LABEL: name: store_common_value_float
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; RV32: liveins: $x10, $x11, $x12, $f16_f
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; RV32-NEXT: {{ $}}
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; RV32-NEXT: $f10_f = FSGNJ_S $f16_f, $f16_f
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; RV32-NEXT: FSW $f10_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV32-NEXT: FSW $f10_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
|
|
; RV32-NEXT: FSW killed $f10_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
|
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; RV32-NEXT: PseudoRET
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; RV64-LABEL: name: store_common_value_float
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; RV64: liveins: $x10, $x11, $x12, $f16_f
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; RV64-NEXT: {{ $}}
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|
; RV64-NEXT: FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV64-NEXT: FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
|
|
; RV64-NEXT: FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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; RV64-NEXT: PseudoRET
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FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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PseudoRET
|
|
|
|
...
|
|
---
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name: store_common_value_double
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|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $x11, $x12, $f16_d
|
|
|
|
; RV32-LABEL: name: store_common_value_double
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|
; RV32: liveins: $x10, $x11, $x12, $f16_d
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|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $f10_d = FSGNJ_D $f16_d, $f16_d
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|
; RV32-NEXT: FSD $f10_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
; RV32-NEXT: FSD $f10_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
|
|
; RV32-NEXT: FSD killed $f10_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
|
|
; RV32-NEXT: PseudoRET
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|
; RV64-LABEL: name: store_common_value_double
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|
; RV64: liveins: $x10, $x11, $x12, $f16_d
|
|
; RV64-NEXT: {{ $}}
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|
; RV64-NEXT: $f10_d = FSGNJ_D $f16_d, $f16_d
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|
; RV64-NEXT: FSD $f10_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
; RV64-NEXT: FSD $f10_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
|
|
; RV64-NEXT: FSD killed $f10_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
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|
; RV64-NEXT: PseudoRET
|
|
FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
|
|
FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: store_common_ptr
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV32-NEXT: $x11 = ADDI $x16, 0
|
|
; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 3
|
|
; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 5
|
|
; RV32-NEXT: SW killed renamable $x10, killed $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV64-NEXT: $x11 = ADDI $x16, 0
|
|
; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 3
|
|
; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 5
|
|
; RV64-NEXT: SW killed renamable $x10, killed $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
renamable $x10 = ADDI $x0, 1
|
|
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
renamable $x10 = ADDI $x0, 3
|
|
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
renamable $x10 = ADDI $x0, 5
|
|
SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_self
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: store_common_ptr_self
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV32-NEXT: $x11 = ADDI $x16, 0
|
|
; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 3
|
|
; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_self
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV64-NEXT: $x11 = ADDI $x16, 0
|
|
; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 3
|
|
; RV64-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q)
|
|
; RV64-NEXT: PseudoRET
|
|
renamable $x10 = ADDI $x0, 1
|
|
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
renamable $x10 = ADDI $x0, 3
|
|
SW killed renamable $x10, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
SW killed renamable $x16, renamable $x16, 0 :: (volatile store (s32) into %ir.q)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_float
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16, $f10_f, $f11_f, $f12_f
|
|
|
|
; RV32-LABEL: name: store_common_ptr_float
|
|
; RV32: liveins: $x16, $f10_f, $f11_f, $f12_f
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x10 = ADDI $x16, 0
|
|
; RV32-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_float
|
|
; RV64: liveins: $x16, $f10_f, $f11_f, $f12_f
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_double
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16, $f10_d, $f11_d, $f12_d
|
|
|
|
; RV32-LABEL: name: store_common_ptr_double
|
|
; RV32: liveins: $x16, $f10_d, $f11_d, $f12_d
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x10 = ADDI $x16, 0
|
|
; RV32-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV32-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV32-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_double
|
|
; RV64: liveins: $x16, $f10_d, $f11_d, $f12_d
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x10 = ADDI $x16, 0
|
|
; RV64-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV64-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV64-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x11 = ADDI $x16, 0
|
|
; RV32-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV32-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV32-NEXT: dead renamable $x10 = LW killed $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: load_common_ptr
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x11 = ADDI $x16, 0
|
|
; RV64-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV64-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV64-NEXT: dead renamable $x10 = LW killed $x11, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
dead renamable $x10 = LW renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
dead renamable $x10 = LW renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr_float
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr_float
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x10 = ADDI $x16, 0
|
|
; RV32-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
|
|
; RV32-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1)
|
|
; RV32-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2)
|
|
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
; RV64-LABEL: name: load_common_ptr_float
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
|
|
; RV64-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
|
|
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
|
|
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
|
|
renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
|
|
renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
|
|
PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr_double
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr_double
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x10 = ADDI $x16, 0
|
|
; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
|
|
; RV32-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
|
|
; RV32-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
|
|
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
; RV64-LABEL: name: load_common_ptr_double
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x10 = ADDI $x16, 0
|
|
; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
|
|
; RV64-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
|
|
; RV64-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
|
|
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
|
|
renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
|
|
renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
|
|
PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
|
|
...
|
|
---
|
|
name: store_large_offset
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: store_large_offset
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 1
|
|
; RV32-NEXT: $x12 = ADDI $x10, 384
|
|
; RV32-NEXT: SW killed renamable $x11, $x12, 16 :: (volatile store (s32) into %ir.0)
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 3
|
|
; RV32-NEXT: SW killed renamable $x11, $x12, 20 :: (volatile store (s32) into %ir.1)
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 5
|
|
; RV32-NEXT: SW killed renamable $x11, $x12, 24 :: (volatile store (s32) into %ir.2)
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 7
|
|
; RV32-NEXT: SW killed renamable $x11, killed $x12, 28 :: (volatile store (s32) into %ir.3)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 1
|
|
; RV64-NEXT: $x12 = ADDI $x10, 384
|
|
; RV64-NEXT: SW killed renamable $x11, $x12, 16 :: (volatile store (s32) into %ir.0)
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 3
|
|
; RV64-NEXT: SW killed renamable $x11, $x12, 20 :: (volatile store (s32) into %ir.1)
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 5
|
|
; RV64-NEXT: SW killed renamable $x11, $x12, 24 :: (volatile store (s32) into %ir.2)
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 7
|
|
; RV64-NEXT: SW killed renamable $x11, killed $x12, 28 :: (volatile store (s32) into %ir.3)
|
|
; RV64-NEXT: PseudoRET
|
|
renamable $x11 = ADDI $x0, 1
|
|
SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
renamable $x11 = ADDI $x0, 3
|
|
SW killed renamable $x11, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
renamable $x11 = ADDI $x0, 5
|
|
SW killed renamable $x11, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
|
|
renamable $x11 = ADDI $x0, 7
|
|
SW killed renamable $x11, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_large_offset_float
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
|
|
|
|
; RV32-LABEL: name: store_large_offset_float
|
|
; RV32: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x11 = ADDI $x10, 384
|
|
; RV32-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0)
|
|
; RV32-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1)
|
|
; RV32-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2)
|
|
; RV32-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset_float
|
|
; RV64: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
; RV64-NEXT: FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
; RV64-NEXT: FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
|
|
; RV64-NEXT: FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
|
|
; RV64-NEXT: PseudoRET
|
|
FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
|
|
FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_large_offset_double
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
|
|
|
|
; RV32-LABEL: name: store_large_offset_double
|
|
; RV32: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x11 = ADDI $x10, 768
|
|
; RV32-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
|
|
; RV32-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
|
|
; RV32-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
|
|
; RV32-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset_double
|
|
; RV64: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x11 = ADDI $x10, 768
|
|
; RV64-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
|
|
; RV64-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
|
|
; RV64-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
|
|
; RV64-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
|
|
; RV64-NEXT: PseudoRET
|
|
FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
|
|
FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
|
|
FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2)
|
|
FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_large_offset
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x12 = ADDI $x10, 384
|
|
; RV32-NEXT: dead renamable $x11 = LW $x12, 16 :: (volatile load (s32) from %ir.0)
|
|
; RV32-NEXT: dead renamable $x11 = LW $x12, 20 :: (volatile load (s32) from %ir.1)
|
|
; RV32-NEXT: dead renamable $x11 = LW $x12, 24 :: (volatile load (s32) from %ir.2)
|
|
; RV32-NEXT: dead renamable $x10 = LW killed $x12, 28 :: (volatile load (s32) from %ir.3)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: load_large_offset
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x12 = ADDI $x10, 384
|
|
; RV64-NEXT: dead renamable $x11 = LW $x12, 16 :: (volatile load (s32) from %ir.0)
|
|
; RV64-NEXT: dead renamable $x11 = LW $x12, 20 :: (volatile load (s32) from %ir.1)
|
|
; RV64-NEXT: dead renamable $x11 = LW $x12, 24 :: (volatile load (s32) from %ir.2)
|
|
; RV64-NEXT: dead renamable $x10 = LW killed $x12, 28 :: (volatile load (s32) from %ir.3)
|
|
; RV64-NEXT: PseudoRET
|
|
dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0)
|
|
dead renamable $x11 = LW renamable $x10, 404 :: (volatile load (s32) from %ir.1)
|
|
dead renamable $x11 = LW renamable $x10, 408 :: (volatile load (s32) from %ir.2)
|
|
dead renamable $x10 = LW killed renamable $x10, 412 :: (volatile load (s32) from %ir.3)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_large_offset_float
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset_float
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x11 = ADDI $x10, 384
|
|
; RV32-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx)
|
|
; RV32-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1)
|
|
; RV32-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2)
|
|
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
; RV64-LABEL: name: load_large_offset_float
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
|
|
; RV64-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
|
|
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
|
|
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
|
|
renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
|
|
renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
|
|
PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
|
|
|
|
...
|
|
---
|
|
name: load_large_offset_double
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset_double
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: $x11 = ADDI $x10, 768
|
|
; RV32-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
|
|
; RV32-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
|
|
; RV32-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
|
|
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
; RV64-LABEL: name: load_large_offset_double
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: $x11 = ADDI $x10, 768
|
|
; RV64-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
|
|
; RV64-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
|
|
; RV64-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
|
|
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
|
|
renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
|
|
renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
|
|
PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
|
|
|
|
...
|
|
---
|
|
name: store_common_value_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: store_common_value_no_opt
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_value_no_opt
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV64-NEXT: PseudoRET
|
|
SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_value_float_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f16_f
|
|
|
|
; RV32-LABEL: name: store_common_value_float_no_opt
|
|
; RV32: liveins: $x10, $f16_f
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_value_float_no_opt
|
|
; RV64: liveins: $x10, $f16_f
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
; RV64-NEXT: PseudoRET
|
|
FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_value_double_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f16_d
|
|
|
|
; RV32-LABEL: name: store_common_value_double_no_opt
|
|
; RV32: liveins: $x10, $f16_d
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_value_double_no_opt
|
|
; RV64: liveins: $x10, $f16_d
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
; RV64-NEXT: PseudoRET
|
|
FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: store_common_ptr_no_opt
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV32-NEXT: SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_no_opt
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $x10 = ADDI $x0, 1
|
|
; RV64-NEXT: SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
renamable $x10 = ADDI $x0, 1
|
|
SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_float_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16, $f10_f
|
|
|
|
; RV32-LABEL: name: store_common_ptr_float_no_opt
|
|
; RV32: liveins: $x16, $f10_f
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_float_no_opt
|
|
; RV64: liveins: $x16, $f10_f
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_common_ptr_double_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16, $f10_d
|
|
|
|
; RV32-LABEL: name: store_common_ptr_double_no_opt
|
|
; RV32: liveins: $x16, $f10_d
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_common_ptr_double_no_opt
|
|
; RV64: liveins: $x16, $f10_d
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr_no_opt
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: load_common_ptr_no_opt
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
; RV64-NEXT: PseudoRET
|
|
dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr_float_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr_float_no_opt
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g)
|
|
; RV32-NEXT: PseudoRET implicit $f10_f
|
|
; RV64-LABEL: name: load_common_ptr_float_no_opt
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g)
|
|
; RV64-NEXT: PseudoRET implicit $f10_f
|
|
renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g)
|
|
PseudoRET implicit $f10_f
|
|
|
|
...
|
|
---
|
|
name: load_common_ptr_double_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x16
|
|
|
|
; RV32-LABEL: name: load_common_ptr_double_no_opt
|
|
; RV32: liveins: $x16
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g)
|
|
; RV32-NEXT: PseudoRET implicit $f10_d
|
|
; RV64-LABEL: name: load_common_ptr_double_no_opt
|
|
; RV64: liveins: $x16
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g)
|
|
; RV64-NEXT: PseudoRET implicit $f10_d
|
|
renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g)
|
|
PseudoRET implicit $f10_d
|
|
|
|
...
|
|
---
|
|
name: store_large_offset_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: store_large_offset_no_opt
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 1
|
|
; RV32-NEXT: SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
; RV32-NEXT: renamable $x11 = ADDI $x0, 3
|
|
; RV32-NEXT: SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset_no_opt
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 1
|
|
; RV64-NEXT: SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
; RV64-NEXT: renamable $x11 = ADDI $x0, 3
|
|
; RV64-NEXT: SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
; RV64-NEXT: PseudoRET
|
|
renamable $x11 = ADDI $x0, 1
|
|
SW killed renamable $x11, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
renamable $x11 = ADDI $x0, 3
|
|
SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_large_offset_float_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f10_f, $f11_f
|
|
|
|
; RV32-LABEL: name: store_large_offset_float_no_opt
|
|
; RV32: liveins: $x10, $f10_f, $f11_f
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
; RV32-NEXT: FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset_float_no_opt
|
|
; RV64: liveins: $x10, $f10_f, $f11_f
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
; RV64-NEXT: FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
; RV64-NEXT: PseudoRET
|
|
FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
|
|
FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: store_large_offset_double_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10, $f10_d, $f11_d
|
|
|
|
; RV32-LABEL: name: store_large_offset_double_no_opt
|
|
; RV32: liveins: $x10, $f10_d, $f11_d
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
|
|
; RV32-NEXT: FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: store_large_offset_double_no_opt
|
|
; RV64: liveins: $x10, $f10_d, $f11_d
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
|
|
; RV64-NEXT: FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
|
|
; RV64-NEXT: PseudoRET
|
|
FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
|
|
FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_large_offset_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset_no_opt
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0)
|
|
; RV32-NEXT: dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1)
|
|
; RV32-NEXT: PseudoRET
|
|
; RV64-LABEL: name: load_large_offset_no_opt
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0)
|
|
; RV64-NEXT: dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1)
|
|
; RV64-NEXT: PseudoRET
|
|
dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0)
|
|
dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: load_large_offset_float_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset_float_no_opt
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
|
|
; RV32-NEXT: renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
|
|
; RV32-NEXT: PseudoRET implicit $f10_f, implicit $f11_f
|
|
; RV64-LABEL: name: load_large_offset_float_no_opt
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
|
|
; RV64-NEXT: renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
|
|
; RV64-NEXT: PseudoRET implicit $f10_f, implicit $f11_f
|
|
renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
|
|
renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
|
|
PseudoRET implicit $f10_f, implicit $f11_f
|
|
|
|
...
|
|
---
|
|
name: load_large_offset_double_no_opt
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x10
|
|
|
|
; RV32-LABEL: name: load_large_offset_double_no_opt
|
|
; RV32: liveins: $x10
|
|
; RV32-NEXT: {{ $}}
|
|
; RV32-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
|
|
; RV32-NEXT: renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
|
|
; RV32-NEXT: PseudoRET implicit $f10_d, implicit $f11_d
|
|
; RV64-LABEL: name: load_large_offset_double_no_opt
|
|
; RV64: liveins: $x10
|
|
; RV64-NEXT: {{ $}}
|
|
; RV64-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
|
|
; RV64-NEXT: renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
|
|
; RV64-NEXT: PseudoRET implicit $f10_d, implicit $f11_d
|
|
renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
|
|
renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
|
|
PseudoRET implicit $f10_d, implicit $f11_d
|
|
|
|
...
|