1fa8fd4c33
This reverts commit 65aaecca8842dec30d03734a7fe8ce33c5afec81. There was an ordering problem in the calculation of the partial remainder. Original commit message: If the divisor is even, we can first shift the dividend and divisor right by the number of trailing zeros. Now the divisor is odd and we can do the original algorithm to calculate a remainder. Then we shift that remainder left by the number of trailing zeros and add the bits that were shifted out of the dividend. Differential Revision: https://reviews.llvm.org/D135541
383 lines
10 KiB
LLVM
383 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen2/i64/g' %s | llc -mtriple=riscv32 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV32
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; RUN: sed 's/iXLen2/i128/g' %s | llc -mtriple=riscv64 -mattr=+m | \
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; RUN: FileCheck %s --check-prefix=RV64
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define iXLen2 @test_urem_3(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_3:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 699051
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; RV32-NEXT: addi a1, a1, -1365
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a2, a1, 1
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; RV32-NEXT: andi a1, a1, -2
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_3:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI0_0)
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; RV64-NEXT: ld a2, %lo(.LCPI0_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a2, a1, 1
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; RV64-NEXT: andi a1, a1, -2
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 3
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_5(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_5:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 838861
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; RV32-NEXT: addi a1, a1, -819
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a2, a1, 2
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; RV32-NEXT: andi a1, a1, -4
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_5:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI1_0)
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; RV64-NEXT: ld a2, %lo(.LCPI1_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a2, a1, 2
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; RV64-NEXT: andi a1, a1, -4
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 5
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_7(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_7:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 7
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __umoddi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_7:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 7
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __umodti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 7
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_9(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_9:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: li a2, 9
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; RV32-NEXT: li a3, 0
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; RV32-NEXT: call __umoddi3@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_9:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: li a2, 9
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; RV64-NEXT: li a3, 0
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; RV64-NEXT: call __umodti3@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 9
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_15(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_15:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 559241
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; RV32-NEXT: addi a1, a1, -1911
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 3
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; RV32-NEXT: slli a2, a1, 4
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_15:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI4_0)
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; RV64-NEXT: ld a2, %lo(.LCPI4_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a1, a1, 3
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; RV64-NEXT: slli a2, a1, 4
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 15
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_17(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_17:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 986895
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; RV32-NEXT: addi a1, a1, 241
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a2, a1, 4
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; RV32-NEXT: andi a1, a1, -16
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_17:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI5_0)
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; RV64-NEXT: ld a2, %lo(.LCPI5_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a2, a1, 4
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; RV64-NEXT: andi a1, a1, -16
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 17
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_255(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_255:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 526344
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; RV32-NEXT: addi a1, a1, 129
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 7
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; RV32-NEXT: slli a2, a1, 8
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_255:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI6_0)
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; RV64-NEXT: ld a2, %lo(.LCPI6_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a1, a1, 7
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; RV64-NEXT: slli a2, a1, 8
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 255
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_257(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_257:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 1044496
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; RV32-NEXT: addi a1, a1, -255
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a2, a1, 8
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; RV32-NEXT: andi a1, a1, -256
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_257:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI7_0)
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; RV64-NEXT: ld a2, %lo(.LCPI7_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a2, a1, 8
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; RV64-NEXT: andi a1, a1, -256
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 257
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_65535(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_65535:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 524296
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; RV32-NEXT: addi a1, a1, 1
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; RV32-NEXT: mulhu a1, a0, a1
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; RV32-NEXT: srli a1, a1, 15
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; RV32-NEXT: slli a2, a1, 16
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_65535:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a2, %hi(.LCPI8_0)
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; RV64-NEXT: ld a2, %lo(.LCPI8_0)(a2)
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: mulhu a1, a0, a2
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; RV64-NEXT: srli a1, a1, 15
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; RV64-NEXT: slli a2, a1, 16
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 65535
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_65537(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_65537:
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; RV32: # %bb.0:
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; RV32-NEXT: add a1, a0, a1
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; RV32-NEXT: sltu a0, a1, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lui a1, 1048560
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; RV32-NEXT: addi a2, a1, 1
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; RV32-NEXT: mulhu a2, a0, a2
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; RV32-NEXT: and a1, a2, a1
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; RV32-NEXT: srli a2, a2, 16
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: sub a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_65537:
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; RV64: # %bb.0:
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; RV64-NEXT: add a1, a0, a1
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; RV64-NEXT: sltu a0, a1, a0
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: lui a1, 983041
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; RV64-NEXT: slli a1, a1, 4
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; RV64-NEXT: addi a1, a1, -1
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; RV64-NEXT: slli a1, a1, 16
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; RV64-NEXT: addi a1, a1, 1
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; RV64-NEXT: mulhu a1, a0, a1
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; RV64-NEXT: lui a2, 1048560
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; RV64-NEXT: and a2, a1, a2
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; RV64-NEXT: srli a1, a1, 16
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: sub a0, a0, a1
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 65537
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ret iXLen2 %a
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}
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define iXLen2 @test_urem_12(iXLen2 %x) nounwind {
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; RV32-LABEL: test_urem_12:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a2, a1, 30
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; RV32-NEXT: srli a3, a0, 2
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; RV32-NEXT: or a2, a3, a2
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; RV32-NEXT: srli a1, a1, 2
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; RV32-NEXT: add a1, a2, a1
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; RV32-NEXT: sltu a2, a1, a2
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: lui a2, 699051
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; RV32-NEXT: addi a2, a2, -1365
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; RV32-NEXT: mulhu a2, a1, a2
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; RV32-NEXT: srli a3, a2, 1
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; RV32-NEXT: andi a2, a2, -2
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; RV32-NEXT: add a2, a2, a3
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; RV32-NEXT: sub a1, a1, a2
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; RV32-NEXT: slli a1, a1, 2
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; RV32-NEXT: andi a0, a0, 3
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; RV32-NEXT: or a0, a1, a0
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_12:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a2, a1, 62
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; RV64-NEXT: srli a3, a0, 2
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; RV64-NEXT: or a2, a3, a2
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; RV64-NEXT: srli a1, a1, 2
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; RV64-NEXT: lui a3, %hi(.LCPI10_0)
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; RV64-NEXT: ld a3, %lo(.LCPI10_0)(a3)
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: sltu a2, a1, a2
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; RV64-NEXT: add a1, a1, a2
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; RV64-NEXT: mulhu a2, a1, a3
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; RV64-NEXT: srli a3, a2, 1
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; RV64-NEXT: andi a2, a2, -2
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; RV64-NEXT: add a2, a2, a3
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; RV64-NEXT: sub a1, a1, a2
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; RV64-NEXT: slli a1, a1, 2
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; RV64-NEXT: andi a0, a0, 3
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; RV64-NEXT: or a0, a1, a0
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; RV64-NEXT: li a1, 0
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; RV64-NEXT: ret
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%a = urem iXLen2 %x, 12
|
|
ret iXLen2 %a
|
|
}
|
|
|