6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
105 lines
3.6 KiB
LLVM
105 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
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declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
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declare {<4 x i32>, <4 x i1>} @llvm.smul.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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; fold (smulo x, 2) -> (saddo x, x)
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define i32 @combine_smul_two(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_smul_two:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %edi, %eax
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; SSE-NEXT: addl %edi, %eax
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; SSE-NEXT: cmovol %esi, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_smul_two:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: addl %edi, %eax
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; AVX-NEXT: cmovol %esi, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %a0, i32 2)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_smul_two(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_smul_two:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: paddd %xmm0, %xmm2
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; SSE-NEXT: movdqa %xmm0, %xmm3
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; SSE-NEXT: pcmpgtd %xmm2, %xmm3
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; SSE-NEXT: pxor %xmm3, %xmm0
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; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_smul_two:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm2
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; AVX-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm3
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; AVX-NEXT: vpxor %xmm3, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.smul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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; fold (umulo x, 2) -> (uaddo x, x)
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define i32 @combine_umul_two(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_umul_two:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %edi, %eax
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; SSE-NEXT: addl %edi, %eax
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; SSE-NEXT: cmovbl %esi, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_umul_two:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: addl %edi, %eax
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; AVX-NEXT: cmovbl %esi, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %a0, i32 2)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_umul_two(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_umul_two:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: paddd %xmm0, %xmm2
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; SSE-NEXT: pmaxud %xmm2, %xmm0
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; SSE-NEXT: pcmpeqd %xmm2, %xmm0
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; SSE-NEXT: blendvps %xmm0, %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_umul_two:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm2
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; AVX-NEXT: vpmaxud %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpcmpeqd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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