6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
175 lines
5.8 KiB
LLVM
175 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86-X87
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
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; Ideally this would compile to 5 multiplies.
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define double @pow_wrapper(double %a) nounwind readonly ssp noredzone {
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; X86-X87-LABEL: pow_wrapper:
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; X86-X87: # %bb.0:
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; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-X87-NEXT: fld %st(0)
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; X86-X87-NEXT: fmul %st(1), %st
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; X86-X87-NEXT: fmul %st, %st(1)
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; X86-X87-NEXT: fmul %st, %st(0)
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; X86-X87-NEXT: fmul %st, %st(1)
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; X86-X87-NEXT: fmul %st, %st(0)
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; X86-X87-NEXT: fmulp %st, %st(1)
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; X86-X87-NEXT: retl
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;
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; X86-SSE-LABEL: pow_wrapper:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: pushl %ebp
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; X86-SSE-NEXT: movl %esp, %ebp
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; X86-SSE-NEXT: andl $-8, %esp
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; X86-SSE-NEXT: subl $8, %esp
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movapd %xmm0, %xmm1
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; X86-SSE-NEXT: mulsd %xmm0, %xmm1
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; X86-SSE-NEXT: mulsd %xmm1, %xmm0
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; X86-SSE-NEXT: mulsd %xmm1, %xmm1
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; X86-SSE-NEXT: mulsd %xmm1, %xmm0
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; X86-SSE-NEXT: mulsd %xmm1, %xmm1
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; X86-SSE-NEXT: mulsd %xmm0, %xmm1
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; X86-SSE-NEXT: movsd %xmm1, (%esp)
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; X86-SSE-NEXT: fldl (%esp)
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; X86-SSE-NEXT: movl %ebp, %esp
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; X86-SSE-NEXT: popl %ebp
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; X86-SSE-NEXT: retl
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;
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; X64-LABEL: pow_wrapper:
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; X64: # %bb.0:
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; X64-NEXT: movapd %xmm0, %xmm1
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; X64-NEXT: mulsd %xmm0, %xmm1
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; X64-NEXT: mulsd %xmm1, %xmm0
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; X64-NEXT: mulsd %xmm1, %xmm1
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; X64-NEXT: mulsd %xmm1, %xmm0
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; X64-NEXT: mulsd %xmm1, %xmm1
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; X64-NEXT: mulsd %xmm1, %xmm0
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; X64-NEXT: retq
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%ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
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ret double %ret
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}
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define double @pow_wrapper_optsize(double %a) optsize {
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; X86-X87-LABEL: pow_wrapper_optsize:
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; X86-X87: # %bb.0:
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; X86-X87-NEXT: subl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 16
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; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-X87-NEXT: fstpl (%esp)
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; X86-X87-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-X87-NEXT: calll __powidf2
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; X86-X87-NEXT: addl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 4
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; X86-X87-NEXT: retl
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;
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; X86-SSE-LABEL: pow_wrapper_optsize:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-SSE-NEXT: calll __powidf2
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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; X64-LABEL: pow_wrapper_optsize:
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; X64: # %bb.0:
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; X64-NEXT: movl $15, %edi
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; X64-NEXT: jmp __powidf2@PLT # TAILCALL
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%ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
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ret double %ret
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}
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define double @pow_wrapper_pgso(double %a) !prof !14 {
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; X86-X87-LABEL: pow_wrapper_pgso:
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; X86-X87: # %bb.0:
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; X86-X87-NEXT: subl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 16
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; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-X87-NEXT: fstpl (%esp)
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; X86-X87-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-X87-NEXT: calll __powidf2
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; X86-X87-NEXT: addl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 4
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; X86-X87-NEXT: retl
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;
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; X86-SSE-LABEL: pow_wrapper_pgso:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-SSE-NEXT: calll __powidf2
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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; X64-LABEL: pow_wrapper_pgso:
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; X64: # %bb.0:
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; X64-NEXT: movl $15, %edi
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; X64-NEXT: jmp __powidf2@PLT # TAILCALL
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%ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
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ret double %ret
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}
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define double @pow_wrapper_minsize(double %a) minsize {
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; X86-X87-LABEL: pow_wrapper_minsize:
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; X86-X87: # %bb.0:
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; X86-X87-NEXT: subl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 16
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; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-X87-NEXT: fstpl (%esp)
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; X86-X87-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-X87-NEXT: calll __powidf2
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; X86-X87-NEXT: addl $12, %esp
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; X86-X87-NEXT: .cfi_def_cfa_offset 4
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; X86-X87-NEXT: retl
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;
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; X86-SSE-LABEL: pow_wrapper_minsize:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: subl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movsd %xmm0, (%esp)
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; X86-SSE-NEXT: movl $15, {{[0-9]+}}(%esp)
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; X86-SSE-NEXT: calll __powidf2
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; X86-SSE-NEXT: addl $12, %esp
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; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE-NEXT: retl
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;
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; X64-LABEL: pow_wrapper_minsize:
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; X64: # %bb.0:
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; X64-NEXT: pushq $15
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; X64-NEXT: .cfi_adjust_cfa_offset 8
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; X64-NEXT: popq %rdi
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; X64-NEXT: .cfi_adjust_cfa_offset -8
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; X64-NEXT: jmp __powidf2@PLT # TAILCALL
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%ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
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ret double %ret
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}
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declare double @llvm.powi.f64.i32(double, i32) nounwind readonly
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"ProfileSummary", !1}
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!1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
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!2 = !{!"ProfileFormat", !"InstrProf"}
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!3 = !{!"TotalCount", i64 10000}
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!4 = !{!"MaxCount", i64 10}
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!5 = !{!"MaxInternalCount", i64 1}
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!6 = !{!"MaxFunctionCount", i64 1000}
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!7 = !{!"NumCounts", i64 3}
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!8 = !{!"NumFunctions", i64 3}
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!9 = !{!"DetailedSummary", !10}
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!10 = !{!11, !12, !13}
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!11 = !{i32 10000, i64 100, i32 1}
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!12 = !{i32 999000, i64 100, i32 1}
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!13 = !{i32 999999, i64 1, i32 2}
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!14 = !{!"function_entry_count", i64 0}
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