189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
87 lines
3.3 KiB
LLVM
87 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE4
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
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define <4 x i64> @PR45808(<4 x i64> %0, <4 x i64> %1) {
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; SSE2-LABEL: PR45808:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
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; SSE2-NEXT: movdqa %xmm3, %xmm5
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; SSE2-NEXT: pxor %xmm4, %xmm5
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; SSE2-NEXT: movdqa %xmm1, %xmm6
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; SSE2-NEXT: pxor %xmm4, %xmm6
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; SSE2-NEXT: movdqa %xmm6, %xmm7
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; SSE2-NEXT: pcmpgtd %xmm5, %xmm7
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; SSE2-NEXT: movdqa %xmm2, %xmm8
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; SSE2-NEXT: pxor %xmm4, %xmm8
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; SSE2-NEXT: pxor %xmm0, %xmm4
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; SSE2-NEXT: movdqa %xmm4, %xmm9
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; SSE2-NEXT: pcmpgtd %xmm8, %xmm9
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; SSE2-NEXT: movdqa %xmm9, %xmm10
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; SSE2-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm7[0,2]
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; SSE2-NEXT: pcmpeqd %xmm5, %xmm6
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; SSE2-NEXT: pcmpeqd %xmm8, %xmm4
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; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm6[1,3]
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; SSE2-NEXT: andps %xmm10, %xmm4
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; SSE2-NEXT: shufps {{.*#+}} xmm9 = xmm9[1,3],xmm7[1,3]
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; SSE2-NEXT: orps %xmm4, %xmm9
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; SSE2-NEXT: pcmpeqd %xmm4, %xmm4
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; SSE2-NEXT: pxor %xmm9, %xmm4
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; SSE2-NEXT: pxor %xmm5, %xmm5
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; SSE2-NEXT: pcmpgtd %xmm4, %xmm5
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; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
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; SSE2-NEXT: pand %xmm4, %xmm0
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; SSE2-NEXT: pandn %xmm2, %xmm4
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; SSE2-NEXT: por %xmm4, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm9[2,1,3,3]
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; SSE2-NEXT: psllq $63, %xmm2
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; SSE2-NEXT: psrad $31, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: pandn %xmm3, %xmm2
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; SSE2-NEXT: por %xmm2, %xmm1
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: PR45808:
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; SSE4: # %bb.0:
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; SSE4-NEXT: movdqa %xmm0, %xmm4
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: pcmpgtq %xmm3, %xmm0
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; SSE4-NEXT: movdqa %xmm4, %xmm5
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; SSE4-NEXT: pcmpgtq %xmm2, %xmm5
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; SSE4-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3]
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; SSE4-NEXT: pcmpeqd %xmm6, %xmm6
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; SSE4-NEXT: pxor %xmm5, %xmm6
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; SSE4-NEXT: psllq $63, %xmm0
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; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm3
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; SSE4-NEXT: pmovsxdq %xmm6, %xmm0
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; SSE4-NEXT: blendvpd %xmm0, %xmm4, %xmm2
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; SSE4-NEXT: movapd %xmm2, %xmm0
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; SSE4-NEXT: movapd %xmm3, %xmm1
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; SSE4-NEXT: retq
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;
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; AVX1-LABEL: PR45808:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
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; AVX1-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
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; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR45808:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
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; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
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; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: retq
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%3 = icmp sgt <4 x i64> %0, %1
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%4 = xor <4 x i1> %3, <i1 true, i1 true, i1 false, i1 false>
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%5 = select <4 x i1> %4, <4 x i64> %0, <4 x i64> %1
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ret <4 x i64> %5
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}
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