Lei Huang 7a7e9109a2 [PowerPC] Implement P10 Byte Reverse Insructions ...

Generate brh, brw and brd instructions for byte-swap operations
on P10 and generating a single instruction for a 32-bit swap followed
by a 16-bit right shift.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D140414

2022-12-21 09:15:57 -06:00

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dcbt.txt

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lit.local.cfg

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p10insts.txt

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ppc32-extpid-e500.txt

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ppc64-encoding-4xx.txt

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ppc64-encoding-6xx.txt

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ppc64-encoding-bookII.txt

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ppc64-encoding-bookIII.txt

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ppc64-encoding-e500.txt

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ppc64-encoding-ext.txt

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ppc64-encoding-fp.txt

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ppc64-encoding-ISA31-invalid.txt

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ppc64-encoding-ISA31.txt

[PowerPC] Implement P10 Byte Reverse Insructions

2022-12-21 09:15:57 -06:00

ppc64-encoding-p8htm.txt

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ppc64-encoding-p8vector.txt

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ppc64-encoding-p9vector.txt

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ppc64-encoding-vmx.txt

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ppc64-encoding.txt

[PowerPC] Set the special DSCR with a compiler option.

2022-03-31 14:06:30 -05:00

ppc64-operands.txt

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ppc64le-encoding-ISAFuture.txt

[PowerPC] Add new load/store with length instructions to Future CPU.

2022-11-21 13:22:27 -06:00

ppc64le-encoding.txt

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ppc-encoding-ISAFuture.txt

[PowerPC] Add new load/store with length instructions to Future CPU.

2022-11-21 13:22:27 -06:00

vsx.txt

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