de5ed0c58e
This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
16 lines
1015 B
ArmAsm
16 lines
1015 B
ArmAsm
# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>%t1
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# RUN: FileCheck %s < %t1
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dmt 4 # CHECK: error: invalid operand for instruction
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dmt $4, $5 # CHECK: error: invalid operand for instruction
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dmt $5, 0($4) # CHECK: error: invalid operand for instruction
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emt 4 # CHECK: error: invalid operand for instruction
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emt $4, $5 # CHECK: error: invalid operand for instruction
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emt $5, 0($5) # CHECK: error: invalid operand for instruction
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dvpe 4 # CHECK: error: invalid operand for instruction
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dvpe $4, $5 # CHECK: error: invalid operand for instruction
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dvpe $5, 0($4) # CHECK: error: invalid operand for instruction
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evpe 4 # CHECK: error: invalid operand for instruction
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evpe $4, $5 # CHECK: error: invalid operand for instruction
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evpe $5, 0($5) # CHECK: error: invalid operand for instruction
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# FIXME: add tests for mftr/mttr.
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