f5c62ee0fa
The insertion point of COPY isn't always optimal and could eventually lead to a worse block layout, see the regression test in the first commit. This change affects many architectures but the amount of total instructions in the test cases seems too be slightly lower.
86 lines
2.6 KiB
LLVM
86 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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%0 = type { double, double, double, i32, i32 }
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declare ptr @malloc() local_unnamed_addr
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define void @phi3(ptr) nounwind {
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; CHECK-LABEL: phi3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -64(1)
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; CHECK-NEXT: std 0, 80(1)
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: bl malloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr 29, 3
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; CHECK-NEXT: bl malloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 6, 30, -4
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; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: addi 4, 29, -8
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: lwzu 8, 4(6)
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; CHECK-NEXT: bdz .LBB0_5
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: extswsli 7, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(6)
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: add 7, 3, 7
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; CHECK-NEXT: stdu 7, 8(4)
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; CHECK-NEXT: extswsli 7, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(6)
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; CHECK-NEXT: bdz .LBB0_4
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: add 9, 3, 7
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; CHECK-NEXT: extswsli 7, 5, 5
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; CHECK-NEXT: add 5, 8, 5
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; CHECK-NEXT: lwzu 8, 4(6)
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; CHECK-NEXT: stdu 9, 8(4)
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; CHECK-NEXT: bdnz .LBB0_3
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: add 6, 3, 7
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; CHECK-NEXT: stdu 6, 8(4)
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: extswsli 5, 5, 5
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; CHECK-NEXT: add 3, 3, 5
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; CHECK-NEXT: stdu 3, 8(4)
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; CHECK-NEXT: addi 1, 1, 64
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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%2 = tail call noalias ptr @malloc()
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%3 = bitcast ptr %2 to ptr
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%4 = tail call noalias ptr @malloc()
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%5 = bitcast ptr %4 to ptr
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br label %6
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6: ; preds = %6, %1
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%7 = phi i64 [ %16, %6 ], [ 0, %1 ]
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%8 = phi i32 [ %15, %6 ], [ 0, %1 ]
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%9 = phi i64 [ %17, %6 ], [ undef, %1 ]
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%10 = sext i32 %8 to i64
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%11 = getelementptr inbounds %0, ptr %5, i64 %10
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%12 = getelementptr inbounds ptr, ptr %3, i64 %7
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store ptr %11, ptr %12, align 8
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%13 = getelementptr inbounds i32, ptr %0, i64 %7
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%14 = load i32, ptr %13, align 4
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%15 = add nsw i32 %14, %8
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%16 = add nuw nsw i64 %7, 1
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%17 = add i64 %9, -1
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%18 = icmp eq i64 %17, 0
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br i1 %18, label %19, label %6
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19: ; preds = %6
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ret void
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}
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