Momchil Velikov d13e223a89

[MLIR][AArch64] Add integration test for lowering of vector.contract to Neon FEAT_I8MM (#144699)

2025-06-26 16:01:00 +01:00

..

Arith/CPU

[mlir][arith][transforms] Adds f4E2M1FN support to truncf and extf (#144157)

2025-06-20 11:27:35 -05:00

Async/CPU

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

Complex/CPU

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

ControlFlow

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

Linalg/CPU

[mlir][linalg] Remove the test-linalg-to-vector-patterns option (#142116)

2025-06-12 19:26:51 +01:00

LLVMIR/CPU

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

Math/CPU

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

MemRef

[mlir][MemRef] Fixed a lit test for assume alignment (#140447)

2025-05-18 15:25:01 +03:00

PDL/CPU

…

SparseTensor

[mlir][SparseTensor] Re-enable tests on AArch64 (#143387)

2025-06-20 14:25:36 +01:00

Standard/CPU

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

Tensor

[mlir][tensor] Add runtime verification for cast/dim/extract/insert/extract_slice (#141332)

2025-06-05 12:06:47 +09:00

Tosa/CPU

[mlir][bufferization][NFC] Rename to_memref to to_buffer (#137180)

2025-05-14 11:17:09 +02:00

Transform

[mlir] introduce debug transform dialect extension (#77595)

2024-01-12 13:24:02 +01:00

Vector

[MLIR][AArch64] Add integration test for lowering of vector.contract to Neon FEAT_I8MM (#144699)

2025-06-26 16:01:00 +01:00